Notes

4/12/01:

The spare boards in B0 will be, starting tomorrow or early next week: CS ID #2, #8, and #15.

Charts (created on 4/2/01):

OK, here's the tally of boards modified so far:
Day / Date Board ID # Modification done
Mon. 3/12/01 5 Capacitor added.
7 Capacitor added.
Thurs. 3/15/01 3 Capacitor added.
6 Capacitor added.
Mon. 3/19/01 4 Capacitor added.
8 Capacitor added.
Thurs. 3/22/01 10 Capacitor added.
11 Capacitor added.
Thurs. 3/29/01 5 Remove test wires.
7 Remove test wires.
Mon. 4/2/01 14 Capacitor added.
1 Capacitor added.
16 Capacitor added.
Tues. 4/10/01 12 Capacitor added.
13 Capacitor added.
Thurs. 4/12/01 2 Capacitor added.
9 Capacitor added.
Fri. 4/13/01 15 Capacitor added.

And here's a chart of the current and historical locations of the boards: (boards that have been modified are written in bold)
CrateSum #: 0 1 2 3 4 5 6 7 8 9 10 11
Day/Date
Tues. 3/13/01 6 3 Before
7 5 After
Fri. 3/16/01 4 8 Before
3 6 After
Tues. 3/20/01 11 10 Before
4 8 After
Fri. 3/23/01a 7 5 Before
11 10 After
Fri. 3/30/01 14 8b Before
5 7 After
As of Mon. 4/2/01 3 5 6 11 10 4 7 Current
Tues. 4/10/01 13 12 Before
14 1 After
Wedn. 4/11/01 9 2 Before
12 13 After
Thurs. 4/12/01 15 Before
9 After
As of Thurs. 4/12/01 3 5 14 1 6 12 13 11 10 9 4 7 Current

Comments:
a: These boards were replaced just so testwires could be removed; the boards had been previously augmented with a capacitor.
b: Is there a problem with ID # 8 after it has been modified? See runs 110191, 192, 193, 195, 204, 212, 220, 231, and 336, for example. Board 8 is currently (4/2/01) in the spare boards crate next to the trigger room.

2/22/01:

Programmed new EPC1 chips to add in Trig_clk8 (not used but connected in the board. Had to reassign a few pins. Chips marked in gold pen. The only difference left is that whereas in the old (10_17_98) program, controller chip D23 was connected to #nTRST, now the pin label for it in the floorplan editor is #TRST. Mircea believes that this is perfectly alright. I'll test it tomorrow.

2/21/01:

Neither the green nor blue chips programmed yesterday work - bunch counters are mismatched by 29 cdf clocks.

2/20/01:

Programmed EPC1 chips, marked in green, to have L1FIFO_Wclk_ET_Sum be delayed by 22ns from the setting that they were in previously.... see your log book for more details. These chips will be tested tomorrow to see if they solve the low-level DAQ buffer error. These chips are labelled as version 3 - "cs_2_20a_01.pof and cs_2_20a_01_1.pof" are the programming files for the chips.

In addition, a set of EPC1 chips, marked in blue, are the original (previous) chips, used for the past year, recompiled afresh. These chips do NOT have the L1FIFO_Wclk_ET_Sum delay incorporated. These chips are version 2 - "cs_2_20_01.pof and cs_2_20_01_1.pof" are the programming files for the chips.

Altera version 9.12 has been used to compile the programs today. (The *.rpt files say version 9.1, but they mean 9.12.) I believe that this was the version used to compile the batch of chips that have been in use for over a year now.

Updated the CrateSum Main Document (functional document). The postscript files referred by the web site now reside in my public_html/CS directory on cdf.uchicago.edu.

Pre - 2/20/01:

The programming files that were used to program the batch of chips in use since the beginning have been in the special "for programming" folder on Shop6 in the e-shop. The names are csum_new.pof and csum_new_1.pof. The date of these files is 3/29/99, although I believe that these programming files were constructed using the control.sof file on Shop8 in E:Nancy/Crate Sum, dated 10/17/98, and the sum.sof file in the same directory, dated 10/14/98 or thereabouts.

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This page is maintained by Nancy J. Lai. Email me at nlai@cdf.uchicago.edu if you have any questions or comments.