CrateSum: Production Log

Status of Production Boards

Last updated Jan. 20, 2000. Details on the tests named here can be found at the here.

Board 1: OK. (Tested prior to Nov. 24.)

Board 2: OK. (Tested prior to Nov. 24.)

Board 3: OK. (Tested prior to Nov. 24.)

Jan. 20: Further 132ns tests passed: 2 loops each of CSTestAll1a through CSTestAll1h (8 tests), and 2 loops each of CSTestAll2 through CSTestAll7 (6 tests). Board also checked for proper handling of the full FIFO condition. The board header word and module ID PROM were verified for correctness.

Board 4: OK. (Tested prior to Nov. 24.)

Board 5: OK.

Nov. 24: Good. Tests: CSTestAll2 through CSTestAll7 on blue.uchicago.edu (6 tests * 8K-events * 10 loops, so approximately half a million events). These tests involve DIRAC boards in all eight slots serviced by CrateSum.

Board 6: OK.

Board 7: OK.

Board 8: OK.

Nov. 24: This board has problems. Soldier bridges between pins on the FIFO chips are suspected. This matter will be investigated further on Monday. These boards seem to be very dirty and there is a white residue on the legs of many FIFO chips.

Nov. 30: The VME interface chip was reprogrammed. The board still fails, although the errors are different now than those encountered on Nov. 24. Some solder paste was found on the back of the board and cleaned. Component U132, the 22ns delay line for the cdf_clock signal, was replaced. The problem still persists.

Jan. 7, 2000: It has been found that for some reason, the cdf_132ns0 signal is not getting to the controller chip. This signal is valid up to the very ball of the BGA chip, but the chip apparently does not see it. An experiment was done in which this signal was rerouted to a different input line; in this case, the board functions fine. The board has been sent back to SMT for replacement of the BGA chip and its return is expected within the next couple of weeks.

Jan. 18: SMT had sent the board out to another company for the replacement of the BGA chip. The board clearly got the cdf_132ns0 signal. After running the board tests, however, it was clear that the front panel output for the trigger sum, bit 2 (counting from zero), was always held high. Upon inspection of the appropriate LVDS chip, it was clear that pins 9 and 10 on U23 were not soldered. After soldering, the board was retested and passed all 132ns tests (i.e. CSTestAll2 through CSTestAll7, 10 loops each).

Board 9: OK.

Nov. 30: The delay line chips' legs were retouched, since some had not been soldered. There were still problems afterwards. A piece of wire was found to be shorting pins 17 and 18 of RC3. These lines correspond to VME data lines, bits 0 and 7. The wire was removed and the board passed all tests CSTestAll2 through CSTestAll7, 10 loops each.

Board 10: OK.

Nov. 29: The delay line pins were retouched. Some of them were clearly not soldered to the pad. The board now works.

Board 11: OK.

Nov. 30: The VME interface chip was reprogrammed.

Jan. 6, 2000: This board had been failing CSTestAll2 and CSTestAll3 while passing CSTestAll4 through CSTestAll7. Trigger bit 8 (counting from 0) of the single-bit trigger bits was, at some specific times, not going to a "1" state. The problem turns out to be that pin 19 of the data latch chip U55 was unsoldered. After soldering, the board passes all tests CSTestAll2 through CSTestAll7.

Board 12: OK.

Board 13: OK.

Nov. 29: The delay line pins were retouched. Some of them were clearly not soldered to the pad. The board now works.

Board 14: OK.

Board 15: OK.

Board 16: Needs work.

Nov. 24: This board clearly has pins that were not soldered by SMT. These pins were left unsoldered, since the plan was to see how its siblings do on the tests. If these boards need to be sent back for reworking, then this present board can be sent as well.

Nov. 30: The VME interface chip was programmed or possibly reprogrammed. The unsoldered pins were soldered and the front panel put on the board. A mounting block is missing from the front panel, so extra care should be exercised while inserting or extracting the board in the crate. The board does not work upon testing.

Jan. 6, 2000: Board passes tests CSTestAll2 through CSTestAll7 with 10 loops each test.

Jan. 20: Further 132ns tests passed: 2 loops each of CSTestAll1a through CSTestAll1h EXCEPT FOR CSTestAll1d (7 tests passed, 1 test failed). 2 loops each of CSTestAll2 through CSTestAll7 (6 tests) passed. Board also checked for proper handling of the full FIFO condition. The board header word and module ID PROM were verified for correctness.

Comments

Nov. 24:

The webbing on the front panel of the Level 1 boards, the purpose of which is to provide good grounding for the boards, may cause problems. They are likely to come loose and get shoved behind the front panel, thus potentially grounding pins on the back of the neighboring board to the right. There is no way, no matter how carefully one inserts the boards, to get around this problem once the webbing starts to lift away from the right edge of the front panel. I think this is a very serious problem that needs to be addressed.

Note (Dec. 1999): Peter Wilson has cleared all L1 boards for removal of the front panel webbing.

Jan. 7:

All boards, with the exception of Boards 1 and 2 at B0, are stored in the temporary storage crate on the shelf in the Chicago e-shop teststand room.

Before the boards are all officially released, I have to run some further tests of the boards to check the module ID prom, the board header word, etc. The board serial numbers of the boards, controlled by DIP switches, also will have to be epoxied.

Jan. 18:

Boards in the temporary storage crate in the chicago e-shop teststand room have had their DIP switches epoxied. All boards have had their front panel webbing removed.

Jan. 20:

Boards 5 and 8 have been tested with the CSTestAll1a through CSTestAll1h tests. The tests CSTestAll2 through CSTestAll7 have been repeated for these boards as well. In addition, proper handling of the full FIFO condition was checked. The board header and ID PROM words were verified.

Boards 4 through 15 (12 boards) are fully tested, packed, and ready to make the journey to Fermilab. The two boards (Boards 1 and 2) currently at B0 will return to Chicago for further testing and work.

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This page is maintained by Nancy J. Lai. Email me at nlai@cdf.uchicago.edu if you have any questions or comments.