FADC board to read out COT ASDQ monitor outputs

This page contains documents, technical data, etc., about the proposed VME Flash ADC board that would digitize signals from a subset of the analog monitor outputs of the COT's ASDQ boards.

Rev B board photos: front and back

Slides from Bill's talk at CDF DAQ meeting, 2000-07-20 (PDF)

Paper presented at IEEE RT2001 conference (Valencia, Spain)

Rough sketch of analog signal path (PDF)

Illustration of cells to be instrumented (and more colorful version)

Famous scope traces of Fe55 pulses recorded at IB4

Aseet's overview of plan for using ASDQ monitor outputs (PDF)

Aseet's schematic for analog repeater board (PDF)

Kevin Pitts's note about COT waveform data (PDF)

Intersil's application note on using fast ADCs (useful even though we plan to use SPT's FADC)

Bill's FADC board project logbook

APEX 20K200 top-level delbuf64.tdf and pin assignments

APEX 20K200 subroutine del64.tdf

APEX 20K200 subroutine buffer64.tdf

ACEX 1K30 top-level capdiv4x8max.tdf and pin assignments

VME interface vme_interface.tdf and pin assignments (note that pin assignments are NOT those used on other Chicago boards)

PCB layout as of 2001-04-16

Schematics as of 2001-04-16:

sheet 1 (PS) (PDF)
sheet 2 (PS) (PDF)
sheet 3 (PS) (PDF)
sheet 4 (PS) (PDF)
sheet 5 (PS) (PDF)
sheet 6 (PS) (PDF)
sheet 7 (PS) (PDF)
sheet 8 (PS) (PDF)
sheet 9 (PS) (PDF)
sheet 10 (PS) (PDF)
sheet 11 (PS) (PDF)
sheet 12 (PS) (PDF)
sheet 13 (PS) (PDF)
sheet 14 (PS) (PDF)
sheet 15 (PS) (PDF)
sheet 16 (PS) (PDF)
sheet 17 (PS) (PDF)
sheet 18 (PS) (PDF)
sheet 19 (PS) (PDF)
sheet 20 (PS) (PDF)
assembly drawing (PS) (PDF)
specification drawing (PS) (PDF)

Peter's schematics for power supply cabling in calorimeter and TDC crates (PDF, PDF)

CDF VIPA crate specification (PDF)

Some very first VME output (!!) 2001-01-29:
(Yes, there are some bugs, some noise issues, etc., but not bad for the second day of prototype testing!)

And now (2001-01-31) finally a decent-looking pulse!! (Pulse height is -230mV, horizontal axis is 2ns/count, leading edge is 5.75ns, trailing edge is 13ns.) But note that the filtering is not yet optimized for noise vs frequency response, etc. (Here is the input pulse.)

2001-02-01: 50 MHz sine wave, after Mircea got noise down below one count, while keeping about 100MHz bandwidth.

2001-02-02: An even better pulse, shown also on the scope, and overlayed.

2001-02-13: First output seen with the COT analog monitor system. The reflections along the input path need some work, but the scope card makes a pretty faithful image of what the scope sees!

2001-06-13: Six-channel Rev B board pulse!

2001-08-10: Four waveforms (A, B, C, D) read out to disk by CDF DAQ in run 123376. From same run, I can also overlay all available pulses for the entire 2usec sample window or for the most interesting 0.5usec window. There are markers every 396 nsec for the CDF BC signal; I don't understand why sometimes the BC marker seems to come one clock early.

2001-08-12: Overlay of many pulses recorded in top three channels of six-channel FADC board in data from run 123608.

2001-08-31: Graphs from Ayana Holloway showing correlations between FADC data and TDC data.
Last updated on $Date: 2001/09/24 23:43:00 $ (UTC)