Sampling chip schedule     Jul 1st 2009

-1 Timing generator
   0.5 Tang

-2 Comparator
   JF/0.5 Herve
   2 weeks

-3 Sampling cell
   0.25 Herve
   1 week

-4 ADC 
   JF/Tang/0.1 Herve


-6 I/O buffers
   JF/0.25Tang
   1 week

-7 Control, overall functionality
   All
   2 weeks

-8 Full layout
   All 

-9 Packaging
   JF

-10 Checks
   All


Submission July 20th