The 16-Channel, 14-BIT 125MHz A/D Board

 

Documentation

 

Option 4 - RJ45 Connectors for the Analog Inputs and Front Panel JTAG Connection
 
SchematicsD - schematics in pdf format.

LayoutD - board fabrication and assembly documentation.

 

 

Option 3 - LEMO Connectors for the Analog Inputs
 
Schematics_LEMO - schematics in pdf format.

Layout_LEMO - board fabrication and assembly documentation.

 

Option 2 - RJ45 Connectors for the Analog Inputs
 
Schematics - schematics in pdf format.

Layout - board fabrication and assembly documentation.

Option 1 - Midas Version
 
Schematics - schematics in pdf format.

Layout - board fabrication and assembly documentation.

 

Prototype

Schematics - Prototype  schematics in pdf format. 

Layout - Prototype board fabrication and assembly documentation.


KOTO Project Related Materials

 

 

 

- Altera project with CL: ADC_125mhz_rev2285.zip

- Altera project with CL: ADC_125mhz_rev2275.zip

- Altera project ADC_125mhz_rev2175.zip

- Altera project with PS: ADC_125mhz_rev2072_with_ADC_sim2017_start_mod_14.zip

 

- Custom DAQ Module for Timing and Energu Measurement for J-Parc E14 - M. Bogdan, J-F. Genat, Y. Wah. - IEEE NPSS Real Time Conference, May 10-15, 2009, Beijing, Paper: PID904380.pdf

- Data Acquisition System for a KL Experiment at J-Parc - M. Bogdan, M. Campbell, J-F. Genat, M. Tecchio, Y. Wah. - TWEPP 2008, Topical Workshop on Electronics for Particle Physics, Naxos, Greece / September 15-19, 2008, Paper: TWEPP08_76.pdf

- Custom 14-Bit, 125MHz ADC/Data processing Module for the Kl Experiment at J-Parc - M. Bogdan, J. Ma, H. Sanders, Y. Wah. 2007 IEEE NSS-MIC Conference Record, N08-6, p.133-134, Oct.27-Nov.3 2007, Honolulu HI, USA. - Slides: PID_N08_6_talk.ppt, Paper: N08-006.pdf

 

 

- Pedestal Subtraction Meeting - 4/5/2016_MI.ppt

- ADC Capacitor Modification Proposal - 12_10_2015_Presentation.pdf

- Current Test of the VCCINT and VCC_PLL Status_Report_10/15/2015.pdf

- Current Test of the VCCINT and VCC_PLL for the 14-BIT ADC Board

- Preliminary Noise and Xtalk Testing of the 14-BIT ADC Board Rev.B - January, 2009: Xtalk_Test_14BIT_ADC_RevB.pdf

- 14-BIT Custom ADC Board Rev.B Status Report - January 9, 2009: SR_01_09_09.pdf

- Crosstalk Test on CsI Front-End Cable - July 11, 2008: Crosstalk_Test.ppt, Crosstalk_Test.pdf, Test_Samples for reference

- 14-BIT Custom ADC Board Rev.B presentation, KEK May 18-20, 2008: 14_BIT_ADC_Board_RevB.ppt, 14_BIT_ADC_Board_RevB.pdf

- Noise Test Results for Rev. A Prototype: test_noise_120.xls (Note: For testing purposes, three channels (N,O,P) are modified to an extended filter bandwidth)

- Update on the E14 Shaper/ADC - February 28, 2008: Update_on_ADC.ppt, Update_on_ADC.pdf

- 14-BIT Custom ADC Board Status Report - August 9, 2007: 14_BIT_ADC_Status_Report.ppt, 14_BIT_ADC_Status_Report.pdf

- 14-BIT Custom ADC Board presentation, Osaka, April 27-29, 2007: 14_BIT_ADC_Board.ppt, 14_BIT_ADC_Board.pdf

- JPARC_DAQ_System presentation, KEK, Dec.9-10, 2006: JPARC_DAQ_System.ppt, JPARC_DAQ_System.pdf

- FADC Boards for Jparc-K preliminary proposal - Nov.16, 2006: fadc_boards_proposal.ppt, fadc_boards_proposal.pdf

 

- 14-BIT ADC Rev.B - Analog Input Channel - Configuration with Offset Adjustment

- 14-BIT ADC Rev.B - Analog Input Channel - Configuration with no Offset

- 14-BIT ADC Rev.A Address Space, Version 0.1, Feb.19, 2008

- Preamp/Shaper/Driver Test Card;

- Breadbord Testing of one Preamp/Shaper/Driver Channel;

- JPARC_DAQ_System presentation, KEK, Dec.9-10, 2006: JPARC_DAQ_System.ppt, JPARC_DAQ_System.pdf

- FADC Boards for Jparc-K preliminary proposal - Nov.16, 2006: fadc_boards_proposal.ppt, fadc_boards_proposal.pdf

- Preliminary test: simulation of existing ATLAS 3in1 Card and the simulation files;
- Comparative simulation results: 3in1 Card vs. 30ns shaper;
 



 
For questions regarding this page contact Mircea Bogdan.
bogdan@edg.uchicago.edu

 

Updated on  April 2017