Trace Analysis

Performed signal integrity tests for some nets on the Q_ADC Board,
using the Interconnect Synthesis tool by Mentor Graphics.
Most of the IBIS models were vendor supplied.
The IBIS model for the FPGA was generated with Quartus II.
 

The following plots show examples of how the signal integrity issues have been addressed for the Q_ADC board.
These are clock lines with 33Ohm series termination placed at the source (TBUSIN and TBUSOUT),
or with 50Ohm/33pF AC termination at the load (CNVST and SCLK).
The signals at the loads, shown with blue on the plots, are monotonic and have no excessive ringing.
  1. TBUSIN [0], [1], [2], [3].
  2. TBUSOUT [0], [1], [2], [3].
  3. CNVST0 with no termination and with ac termination.
  4. SCLK0 with no termination and with ac termination.

 
For questions regarding this page contact Mircea Bogdan.
bogdan@frodo.uchicago.edu
Revised:March, 2005