Revision 0.2
05/13/2013
Mircea Bogdan
The University of Chicago
This Multiplexer Board is a 6U Monsoon Transition Module, designed to work with the Monsoon Clock Board Version 2.
The Monsoon Clock Board generates 32 separate signals (the clocks), wich can be used to independently control 3 CCDs. This Multiplexer Board received these clocks, and uses them to control up to 16 CCDs, one after the other.
The Block Diagram of the Multiplexer Board in presented in Figure 1.
Two sets of 12 signals [buses Read(11:0) and Static(11:0)] are successively applied to each CCD. Bus Read(11:0) is applied to a CCD during the readout time, and bus Static(11:0) is applied to a CCD during the acquisition time. Switching is controlled with signals from bus Ctrl(7:0).
Using this method, one can control up to 256 CCDs with clocks produced by one single Monsoon Clock Board. This prototype Multiplexer Board uses only bits (3:0) to control up to16 CCDs.
Each signal from bus Read(11:0) is buffered 1 -> 4 -> 16 before being applied to the switches. Each signal from bus Static(11:0) goes directly to all 16 switches.
Bit Mapping for the Readout Bus (see also Monsoon Clock Board Manual, Table 7 - Group A).
Note: After multiplexing, bits H2, SW, RG are duplicated (See Buffer/Fanout Schematic). There are 15 bits applied to each CCD (See CCD Cable Connectors Schematic).
| Read(11:0) Pin | 11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Read(11:0)PinName | N_Guard |
H2 |
SW |
RG |
H3U |
H3L |
H1U |
H1L |
TG |
V3 |
V2 |
V1 |
| Clock Board Signal | N_Guard |
H2 |
SW_A |
RG_A |
H3U_A |
H3L_A |
H1U_A |
H1L_A |
TG_A |
V3_A |
V2_A |
V1_A |
| Clock Register Pin | 31 |
30 |
17 |
16 |
15 |
14 |
13 |
12 |
3 |
2 |
1 |
0 |
| J4/J5 Pin Number | J4_E1 |
J5_B2 |
J4_D11 |
J4_E5 |
J4_A5 |
J4_C1 |
J4_A3 |
J4_A1 |
J5_D2 |
J4_C9 |
J4_B1 |
J4_B7 |
Bit Mapping for the Static Bus (see also Monsoon Clock Board Manual, Table 7 - Group B and C).
Note: After multiplexing, bits H2, SW, RG are duplicated (See Buffer/Fanout Schematic). There are 15 bits applied to each CCD (See CCD Cable Connectors Schematic).
| Static(11:0) Pin | 11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Static(11:0)PinName | N_Guard |
H2 |
SW |
RG |
H3U |
H3L |
H1U |
H1L |
TG |
V3 |
V2 |
V1 |
| Clock Board Signal | SW_C |
RG_C |
SW_B |
RG_B |
H3U_B |
H3L_B |
H1U_B |
H1L_B |
TG_B |
V3_B |
V2_B |
V1_B |
| Clock Register Pin | 29 |
28 |
23 |
22 |
21 |
20 |
19 |
18 |
7 |
6 |
5 |
4 |
| Pin Number | J5_D11 | J5_D10 | J4_E24 | J4_E15 | J5_A2 | J4_A21 | J5_E2 | J4_B23 | J4_D15 | J4C18 | J4_C20 | J4_A17 |
Bit Mapping for the Switch Control Bus (see also Monsoon Clock Board Manual, Table 7 - Group C).
Note: Only bits (3:0) are used (See Decoder Schematic).
| Control(7:0) pin | 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Clock Board Signal | H3U_C |
H3L_C |
H1U_C |
H1L_C |
TG_C |
V3_C |
V2_C |
V1_C |
| Clock Register Pin | 27 |
26 |
25 |
24 |
11 |
10 |
9 |
8 |
| Pin Number | J5_A19* |
J5_B14* |
J5_C10* |
J5_A7* |
J5_C7 |
J5_D5 |
J4_B24 |
J5_B11 |
(*) - These clocks are not used.
The rest of the signals from connectors J4 and J5 are not used.
The 16 CCDs are interfaced with two pairs of the same connectors (QSH-060-01-L-D-DP-A and QSH-080-01-L-D-DP-A) as in the old DECam Front End Electronics Transition Module. The first pair is wired for 9 CCDs, exactly like in the old card, so that this new Multiplexer Module can dirrectly replace the old Transition Module. The change between the old Transition Module and the new Multiplexer Module should require only software modification.