Rear Transition Card with VME Access Capabilities

Schematics


  1. 2743_Sheet_1.pdf : Top Level
  2. 2743_Sheet_2.pdf : VME Interface
  3. 2743_Sheet_3.pdf : RP2 Connector
  4. 2743_Sheet_4.pdf : Data Output
  5. 2743_Sheet_5.pdf : Rx FPGA
  6. 2743_Sheet_6.pdf : RP0 Connector
  7. 2743_Sheet_7.pdf : RP3 Buffers
  8. 2743_Sheet_8.pdf : Tx FPGA
  9. 2743_Sheet_9.pdf : RP3 Connector
  10. 2743_Sheet_10.pdf : Data Input
  11. 2743_Sheet_11.pdf : Power Block - general
  12. 2743_Sheet_12rx.pdf, 2743_Sheet_12tx.pdf : Power Blocks for the FPGAs.

     



 
For questions regarding this page contact Mircea Bogdan.
bogdan@edg.uchicago.edu

Revised: August 2011