rcfg_enable |
0 |
rcfg_jtag_enable |
0 |
rcfg_separate_avmm_busy |
0 |
set_capability_reg_enable |
0 |
set_user_identifier |
0 |
set_csr_soft_logic_enable |
0 |
rcfg_file_prefix |
altera_xcvr_atx_pll_s10 |
rcfg_sv_file_enable |
0 |
rcfg_h_file_enable |
0 |
rcfg_mif_file_enable |
0 |
rcfg_multi_enable |
0 |
set_rcfg_emb_strm_enable |
0 |
rcfg_reduced_files_enable |
0 |
rcfg_profile_cnt |
2 |
rcfg_profile_select |
1 |
rcfg_profile_data0 |
|
rcfg_profile_data1 |
|
rcfg_profile_data2 |
|
rcfg_profile_data3 |
|
rcfg_profile_data4 |
|
rcfg_profile_data5 |
|
rcfg_profile_data6 |
|
rcfg_profile_data7 |
|
message_level |
error |
prot_mode |
Basic |
bw_sel |
high |
refclk_cnt |
1 |
refclk_index |
0 |
primary_pll_buffer |
GX clock output buffer |
enable_8G_path |
1 |
enable_28G_output_frm_abv_atx |
0 |
enable_28G_output_frm_blw_atx |
0 |
enable_28G_local_atx_path |
0 |
enable_28G_input_frm_abv_atx |
0 |
enable_28G_input_frm_blw_atx |
0 |
enable_GXT_out_buffer_abv |
0 |
enable_GXT_out_buffer_blw |
0 |
enable_GXT_clock_source |
disabled |
enable_pcie_clk |
0 |
enable_atx_to_fpll_cascade_out |
0 |
set_output_clock_frequency |
1250.0 |
output_clock_datarate |
2500.0 |
set_auto_reference_clock_frequency |
125.0 |
select_manual_config |
false |
m_counter |
40 |
ref_clk_div |
1 |
l_counter |
8 |
usr_analog_voltage |
1_0V |
enable_mcgb |
1 |
mcgb_div |
1 |
enable_hfreq_clk |
1 |
enable_mcgb_pcie_clksw |
0 |
enable_mcgb_reset |
0 |
mcgb_aux_clkin_cnt |
0 |
mcgb_in_clk_freq |
1250.0 |
mcgb_out_datarate |
2500.0 |
enable_bonding_clks |
0 |
pma_width |
64 |
gui_parameter_list |
L cascade predivider/VCO divider(valid in cascade mode) ,L counter (valid in non-cascade mode),L cascade counter (valid in cascade mode),M counter,K counter (valid in fractional mode),N counter,PLL output frequency,vco_freq,datarate |
gui_parameter_values |
select_vco_output,8,0,40,1,1,1250.0 MHz,10000.0 MHz,2500.0 Mbps |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |