Clock Settings for the KOTO OFC Module

Mircea Bogdan
10/7/2019

In the TOP_CDT_81 Reference Design, there are five ClockSwitchControl Outputs, all set to H. If this is changed, then the jumper function described below will change also.




There are 8 LVDS clocks:

CLOCKIN_0, CLOCKIN_2, CLOCKIN_4, CLOCKIN_6 are the Local Clock when Jumper F46 is installed, and change to System Clock when F46 is not installed.


CLOCKIN_1, CLOCKIN_3, CLOCKIN_5, CLOCKIN_7 are always Local Clock.


In the TOP_CDT_81 Reference Design, there are 4 different internal PLLS, each with two Clock Inputs and one Switch Input.


The 8 LVDS clocks go to the FPGA, as follows:

CLOCKIN_0, CLOCKIN_2, CLOCKIN_4, CLOCKIN_6 go to the refclk inputs of the PLLs, which are active when the corresponding ClockSwitch pin in L, i.e. there is no Jumper installed.

CLOCKIN_1, CLOCKIN_3, CLOCKIN_5, CLOCKIN_7 go to the refclk1 inputs of the PLLs, which are active when the corresponding ClockSwitch pin in H, i.e. Jumper is installed.

Jumpers:
F96  - ClockSwitch_0
F104 - ClockSwitch_1
F110 - ClockSwitch_2
F116 - ClockSwitch_3


Exemples:

When working on Local Clock: only install Jumper F46.
When sampling on System Clock with VME running on Local Clock: only install F104.
When no jumper is installed: it all runs on System Clock.