Schematics of the Pulsar board


  1. sheet1.pdf : Top level diagram
  2. sheet2.pdf : Logic_ch_0
  3. sheet3.pdf : Mezzanine Card 1
  4. sheet4.pdf : Mezzanine Card 2
  5. sheet5.pdf : Logic_ch_1
  6. sheet6.pdf : Mezzanine Card 3
  7. sheet7.pdf : VME Interface
  8. sheet8.pdf : P 1
  9. sheet9.pdf : P0
  10. sheet10.pdf : VME Chip
  11. sheet11.pdf : P2
  12. sheet12.pdf : Mezzanine Card 4
  13. sheet13.pdf : Level 1 Inputs
  14. sheet14.pdf : P3
  15. sheet15.pdf : Control
  16. sheet16.pdf : Level 1 Out
  17. sheet17.pdf : TS I/O
  18. sheet18.pdf : Power
  19. sheet19.pdf : SVT/XTRP Out
  20. sheet20.pdf : Clocks
  21. sheet21.pdf : SVT/XTRP In
  22. sheet22.pdf : SVT/XTRP FIFO 0
  23. sheet23.pdf : SVT/XTRP FIFO 1
  24. sheet24.pdf : SVT/XTRP FIFO 2
  25. sheet25.pdf : JTAG Chain
  26. shett1_25.pdf : The whole thing.


 
For questions regarding this page contact Mircea Bogdan.
bogdan@frodo.uchicago.edu
Revised: August 13, 1999