Trace Analysis

1. CDFclkBus1_0.pdf
2. CDFclkBus1_1.pdf
3. Logic2_CDFCLK.pdf
4. Logic2_F1data0.pdf
5. Logic2_F1data1.pdf
6. Logic2_F1data30.pdf
7. Logic2_F1data31.pdf
8. Logic2_F2data0.pdf
9. Logic2_F2data1.pdf
10. Logic2_F2data30.pdf
11. Logic2_F2data31.pdf
12. Logic2_FIFO_emptyA0_n.pdf
13. Logic2_FIFO_emptyA1_n.pdf
14. Logic2_FIFO_emptyA2_n.pdf
15. Logic2_FIFO_emptyA3_n.pdf
16. Logic2_FIFO_emptyB0_n.pdf
17. Logic2_FIFO_emptyB1_n.pdf
18. Logic2_FIFO_emptyB2_n.pdf
19. Logic2_FIFO_emptyB3_n.pdf
20. Logic2_FPGASVT_Ctrl_rdclk.pdf
21. Logic2_FPGAWRclkA.pdf
22. Logic2_FPGAWRclkB.pdf
23. Logic2_L1_IN_DS_0.pdf
24. Logic2_L1_IN_DS_1.pdf
25. Logic2_LCLK1.pdf
26. Logic2_LCLK2.pdf
27. Logic2_LCTRL1_n_in.pdf
28. Logic2_LCTRL2_n_in.pdf
29. Logic2_LWEN1_n_in.pdf
30. Logic2_LWEN2_n_in.pdf
31. Logic2_Roboclock.pdf
32. Logic2_SLINK40MHzClk.pdf
33. Logic2_SRAM_Clk.pdf
34. Logic2_SVT_Ctrl_reset.pdf
35. Logic2_SVT_IN0.pdf
36. Logic2_SVT_IN22.pdf
37. Logic2_SVT_status_DS_n.pdf
38. Logic2_SVT_status_afull_n.pdf
39. Logic2_SVT_status_empty0_n.pdf
40. Logic2_SVT_status_empty1_n.pdf
41. Logic2_SVT_status_full_n.pdf
42. Logic2_UCLK.pdf
43. Logic2_UCTRL_n.pdf
44. Logic2_UWEN_n.pdf