Hello,

After the Monday meeting, we modified the XFT block design (inside the TDC chip)
to follow the functionality described in both notes:

[1]- XTC: The COT TDC Mezzanine Card,Ver1.0,June 11,1998,CDFxxxx;
[2]- Specification for XFT Frontend,Ver1.0,March 4th,2003(blw).

This is where we are right now:

There are 6 continuous but non-overlapping time windows [2]
programmable in units of 12ns and with the edges measured relative
to a calibrated t0 time interval.
The hit detection procedure is to locate 4 sequential high cells
in the input data stream (4.8ns).

The first 3 time windows correspond to the PROMPT, NOTSURE and LATE
windows[1] from the old design and the resulting P3 output data:
"XFT-Hit Bin 0" and "XFT-Hit Bin 1" [2]
are the PROMPT and DELAYED bits [1] and follow
the same truth table (Table2. page 5 from [1]).

In the old design the CDF_CLK is delayed with t0=70ns to bring
it in sync with the earliest possible time at which valid data
could arrive from the current crossing.
The delay is adjustable in 1ns increments [1].
Then the Prompt/Delayed bits are sent out beginning with the NEXT,
delayed(with 70ns) CDF_CLK.

In the new design we have to add some 48ns to t0 in order to
account for the delay inherent to the STRATIX SERDES block.
We will delay CDF_CLK and all the backplane signals (CDF_BC,CDF_B0,
CDF_L1A, CDF_L2A, etc) with 0 to 12 ns, using  delay lines
outside the chip and
account for the rest of t0 (some 108ns) by shifting the edges
of the time windows in steps of 12 ns.
We will send data out P3 beginning with the SECOND
delayed(with 0-12ns) CDF_CLK.

We send out the PROMPT/DELAYED bits (first six words) followed
by XFT-Hit Bin2,3,4,5 (12 more words) as per [1] and [2].

So, any observations are more than welcome.

Thanks,

Mircea