Schematics of the TDC board


  1. sheet1.pdf : Top level diagram
  2. sheet2.pdf : VME_Interface
  3. sheet3.pdf : VME-P1
  4. sheet4.pdf : VME-Chip
  5. sheet5.pdf : VME-P0
  6. sheet6.pdf : VME-P2
  7. sheet7.pdf : FP Connector 1
  8. sheet8.pdf : FP Connector 2
  9. sheet9.pdf : Stratix Chip 0
  10. sheet10.pdf : Clock Buffer
  11. sheet11.pdf : ID_SW & Test Conn
  12. sheet12.pdf : Power
  13. sheet13.pdf : FP Connector 3
  14. sheet14.pdf : P3 Connector
  15. sheet15.pdf : Stratix Chip 1
  16. sheet16.pdf : FP Connector 4


 
For questions regarding this page contact Mircea Bogdan.
bogdan@frodo.uchicago.edu
Revised: Jan. 2004