Just FYI, this is what the EPLD code contains so far for the tower coincidence board.
        97 - 16 bit scalers
               96 for the individual tower singles rates
                1 for the trigger count
          1 - 48 bit trigger pattern word stored in a 5 deep fifo
               one bit is set for each of the 48 possible coincidences that could initiate a trigger
          1 - 12 bit dac latch word

VME NULL write addresses
          cscaler - clears all scalers and the fifo
          escaler - enables all scalers and the fifo
          dscaler - disables all scalers and the fifo

VME write addresses
          wdac - latches a 12 bit dac value
          sdac - strobes the latched dac value into 1 or more of the 8 dacs
                     depending on the word written
          scalersel - select which scaler is read out in subsequent read operation

VME read address
          rscaler - reads out selected 16 bit scaler
          rtrig1 - fetches the next fifo word and sends bits 15 ..0 out on read cycle
          rtrig2 - sends out bits 31..16 out on read cycle
          rtrig3 - sends out bits 47..32 out on read cycle

The input tower signals are stretched to a minimum of 37.5 ns (1.5 clock cycles) before
the coincidence logic.  If we want to do a different coincidence pattern it will
take a reprograming of the EPLD.  This can be easily done from a notebook computer
via a byteblaster cable provided the code has been worked out in advance.  For instance
one could easily combine towers into groups of 4 and then do the coincidence.  This would
give a higher trigger rate but most tracks would not go as near the interaction point.

                                                   Kelby