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\begin{document}

\pagenumbering{arabic}

\begin{titlepage}

\begin{flushright}
CDF/DOC/TRIGGER/4225  \\
Version 2.2 \\
Sept 26, 2005 \\
\end{flushright}

\begin{center}
\ \\[2.in]
{\large \bf DIRAC --- The FINAL Specification}\\
John Wahl and Pedro Amaral\\
University of Chicago \\
Update to V2.2 by Peter Wilson \\
Fermilab \\
\end{center}

\begin{abstract}
This note describes the Digital Information Receive and Compare
(DIRAC) board.  DIRAC is the Run II replacement for the Run I
RAW/CAS boards.  DIRAC is the core processor for the Level 1
calorimetry trigger.  The expected inputs and outputs of the board
are specified.  The sequence of operations performed on the input
signals to produce the output signals is discussed.  The VMEbus
addressing of the DIRAC board is specified. Appendix B specifies all 
the info that needs to be downloaded before a Cold Start.

Note revision 2.2 made to correct description of HAD\_EM\_SEL in Control\_1 
which has opposite behavior from previous documentation.  Also add details 
describing Sum $E_T$\ path including two new tables and bug in implementation
of two tower sum (Section~3.10 and Appendix~C). 
\end{abstract}



\end{titlepage}

\eject

\section{Purpose}

Currently, collisions occur approximately every 3 years at the B$0$
collision hall.  With the completion of the Main Injector upgrade, a
collision may occur every $132 \mbox{ns}$.  The previous level 1
trigger was not able to function at this speed.  Therefore, a new
level 1 trigger must be designed to meet this challenge.  A general
knowledge of the RUN II trigger system is assumed.  If anything is
unclear refer to the documents referenced in the confusing section.
If there are no documents referenced, pray.

\section{Level 1 DIRAC Inputs and Outputs}

\subsection{Detector Information}

Run II is the first collider run at the new bunch crossing time of
132ns.  For Run II the Front-end electronics (FE) and the level 1
(L1) trigger are being replaced. (Among many others) The new L1
trigger expects digital signals from the FE ADMEM boards on the
detector.\cite{ADMEM} DIRAC accepts a 10 bit word for each trigger
tower ($15^{\circ} \phi \times 0.2 \eta$).  Each card processes 6
EM and 6 HAD trigger towers from a quarter of the same wedge in
$\phi$.\cite{tow seg} Therefore, each card receives 120 bits from
the detector.  There are 16 DIRAC cards in a crate, so each crate
receives 1920 signals from 4 wedges of the detector.  (Figure
\ref{crate})

\begin{figure}[p]
\begin{center}
% \epsfig{figure=plots/VME_crate.eps}%, width=6.2in}
 \hbox{%\hspace{0.5in}
  \epsfxsize=\textwidth\epsffile{plots/VME_crate.eps}}
\end{center}
\caption{L1 Calorimetry Crate for DIRAC and Crate Sum}
\label{crate}
\end{figure}

\clearpage

\subsection{The Crate}

There are 2 backplanes in each crate.  The upper backplane is a CDF
standard backplane.\cite{CDF BP} On the upper backplane are 3
connectors for each slot.  The top connector is the standard 5-row
VME-P P$1$.\cite{VME-P BP} The middle connector on the upper
backplane is a special VME-P power connector, P$0$.\cite{VME-P BP}
The lower connector, P2, is a hybrid.  The middle row of signals on
P2 are the standard VME lines.  The outer four rows carry global CDF
control signals and extra power on pins unused by VME.\cite{crate
spec} The DIRAC boards are designed to respond to the VMEbus
protocol for downloading information at the beginning of a run, DAQ
readout and diagnostics.  The second backplane, P3, is custom.  An
auxillary card (AUX) which receives the 120 differential detector
signals(for a total of 240) plugs into P3 from the rear of the
crate.\cite{AUX} The AUX card converts the 120 differential signals
to single ended signals and passes them to DIRAC through P3.  All
trigger tower signals are required to arrive at DIRAC at the same
time.

There is one Crate Sum (CS) board per eight DIRAC 
boards.\cite{dave csum} 
CS receives an 8 bit $\Sigma$E$_{\mbox{T}}$ and 16 bit trigger
summary from each DIRAC card across the P3 backplane.  This means that
the P3 backplane must be at least 192 bits (192 signals from the 8
DIRAC boards) wide for CS and at least 144 bits (24 signals to CS +
120 signals from the AUX card) for DIRAC(this does not include ground
pins).  The pin configuration for DIRAC's P3 is shown in Table
\ref{p3}.  For the CS's pin configuration on P3 see Trigger note
91.\cite{dave csum}

\begin{table}
\centering
\caption{P3 Backplane Pin Assignments}
\label{p3}
$$
\begin{array}{|c||c|c|c|c|c|} \cline{2-6}
\multicolumn{1}{c}{}  & \multicolumn{5}{|c|}{\mbox{Column}} \\ \hline
\mbox{Row} & \mbox{A} & \mbox{B} & \mbox{C} & \mbox{D} & 
    \mbox{E} \\ \hline \hline
1 & \mbox{ground} & \mbox{TRSUM(0)} & \mbox{TRSUM(1)}  & \mbox{TRSUM(2)}  & 
    \mbox{TRSUM(3)} \\ \hline
2 & \mbox{NC} & \mbox{TRSUM(4)} & \mbox{TRSUM(5)}  & \mbox{ground}  & 
    \mbox{TRSUM(6)} \\ \hline
3 & \mbox{NC} & \mbox{TRSUM(7)} & \mbox{ground}  & \mbox{TRSUM(8)}  & 
    \mbox{TRSUM(9)} \\ \hline
4 & \mbox{NC} & \mbox{TRSUM(10)} & \mbox{TRSUM(11)}  & \mbox{ground}  & 
    \mbox{TRSUM(12)} \\ \hline
5 & \mbox{ground} & \mbox{TRSUM(13)} & \mbox{ground}  & \mbox{TRSUM(14)}  & 
    \mbox{TRSUM(15)} \\ \hline
6 & \mbox{NC} & \mbox{TOWIN(0)} & \mbox{TOWIN(1)}  & \mbox{TOWIN(2)}  & 
     \mbox{TOWIN(3)} \\ \hline
7 & \mbox{NC} & \mbox{TOWIN(4)} & \mbox{TOWIN(5)}  & \mbox{ground}  & 
     \mbox{TOWIN(6)} \\ \hline
8 & \mbox{NC} & \mbox{TOWIN(7)} & \mbox{TOWIN(8)}  & \mbox{TOWIN(9)}  & 
     \mbox{TOWIN(10)} \\ \hline
9 & \mbox{ground} & \mbox{TOWIN(11)} & \mbox{ground}  & \mbox{TOWIN(12)}  & 
     \mbox{TOWIN(13)} \\ \hline
10 & \mbox{NC} & \mbox{TOWIN(14)} & \mbox{TOWIN(15)}  & \mbox{TOWIN(16)}  & 
     \mbox{TOWIN(17)} \\ \hline
11 & \mbox{NC} & \mbox{TOWIN(18)} & \mbox{TOWIN(19)}  & \mbox{ground}  & 
     \mbox{TOWIN(20)} \\ \hline
\vdots & \multicolumn{5}{|c|}{\vdots} \\ \hline
38 & \mbox{NC} & \mbox{TOWIN(112)} & \mbox{TOWIN(113)} & \mbox{TOWIN(114)}  & 
     \mbox{TOWIN(115)} \\ \hline
39 & \mbox{NC} & \mbox{TOWIN(116)} & \mbox{TOWIN(117)} & \mbox{ground}  & 
     \mbox{TOWIN(118)} \\ \hline
40 & \mbox{NC} & \mbox{TOWIN(119)} & \mbox{AUX\_SUM\_EN0} & 
     \mbox{ET\_SUM(0)} & \mbox{ET\_SUM(1)} \\ \hline
41 & \mbox{ground} & \mbox{ET\_SUM(2)} & \mbox{AUX\_SUM\_EN1} & 
     \mbox{ET\_SUM(3)} & \mbox{ET\_SUM(4)} \\ \hline
42 & \mbox{NC} & \mbox{ET\_SUM(5)} & \mbox{ET\_SUM(6)} & 
     \mbox{ground} & \mbox{ET\_SUM(7)} \\ \hline
43 & \mbox{NC} & \mbox{NC} & \mbox{AUX\_ENABLE} & \mbox{NC} & 
     \mbox{NC} \\ \hline
44 & \mbox{NC} & \mbox{NC} & \mbox{NC} & \mbox{NC} & 
     \mbox{NC} \\ \hline
\end{array}
$$
\end{table}

\clearpage

\subsection{Tracking Input}

We allow information from the Extra Fast Tracking (XFT) system to be
used in a L1 calorimetry decision.\cite{xft} Eight bits per
15$^{\circ}$ in $\phi$ are received differentially through a front
panel connector from XFT via the eXTRaPolation (XTRP) boards (see
Table \ref{fp4}).  These 8 bits are refer to 8 thresholds defined on
the XTRP boards.  The 8 bits are sent to 3 SRAM's that decode the
information into 3 bits per trigger tower.  DIRAC can decode the
information regardless of the meaning of the triggers used to set
the 8 bits.  Only the DIRAC boards examining the Central and Plug
calorimeter data receive tracking data.  The same data is sent to
each DIRAC card in a $\phi$ slice.  For a crate there are 32 (4
$\phi$ slices $\times$ 8) bits from the XTRP.  This information
arrives at time t$_{\mbox{Tracking}}$ after the bunch crossing.

\begin{table}
\centering
\caption{Front Panel Connector 4 -- Tracking Bits.}
\label{fp4}
$$
\begin{array}{|c|c|c|c|} \hline
\mbox{Pin} & \mbox{Signal} & \mbox{Pin} & \mbox{Signal} \\ \hline \hline
1 & \mbox{Bit 0-} & 2 & \mbox{Bit 0+} \\ \hline
3 & \mbox{Bit 1-} & 4 & \mbox{Bit 1+} \\ \hline
5 & \mbox{Bit 2-} & 6 & \mbox{Bit 2+} \\ \hline
7 & \mbox{Bit 3-} & 8 & \mbox{Bit 3+} \\ \hline
9 & \mbox{Bit 4-} & 10 & \mbox{Bit 4+} \\ \hline
11 & \mbox{Bit 5-} & 12 & \mbox{Bit 5+} \\ \hline
13 & \mbox{Bit 6-} & 14 & \mbox{Bit 6+} \\ \hline
15 & \mbox{Bit 7-} & 16 & \mbox{Bit 7+} \\ \hline
\end{array}
$$                                     
\end{table}

\clearpage

\subsection{Bit/Byte Blaster Input}

To facilitate reprogramming of the EPLDs resident on Dirac, we have
implemented Altera's In System Programmablility (ISP).\cite{altera
ISP} This allows most, but not all the Altera EPLDs on Dirac to be
soldered and still be reprogrammed at a future date.  See the detailed
Dirac document for details on reprogramming.\cite{Dirac Detailed} The
Bit Blaster (or Byte Blaster) connector is a 10 pin connector on Dirac's front panel and
the definition of the bits is shown in table \ref{fpBB}.\cite{altera
BB}

\begin{table}
\centering
\caption{Front Panel Connector 5 -- Bit Blaster}
\label{fpBB}
$$
\begin{array}{|c||c|c|} \cline{2-3}
\multicolumn{1}{c}{}  & \multicolumn{2}{|c|}{\mbox{Column}} \\ \hline
\mbox{Row} & \mbox{A} & \mbox{B} \\ \hline \hline
1 & \mbox{TCK} & \mbox{GND} \\ \hline
2 & \mbox{TDO} & \mbox{VCC} \\ \hline
3 & \mbox{TMS} & \mbox{NC} \\ \hline
4 & \mbox{NC}  & \mbox{NC} \\ \hline
5 & \mbox{TDI} & \mbox{GND} \\ \hline
\end{array}
$$                                     
\end{table}

\clearpage

\section{Board Modules}

Figure \ref{top level} shows a block level diagram of DIRAC.  The
module {\bf Towers} contains 6 copies of the L1 decision electronics
and as shown in figure \ref{tower}.  Objects in bold face within this
document are names of modules or signals in figure \ref{top level} or
\ref{tower}.

\begin{figure}[p]
\begin{center}
% \epsfig{figure=plots/top_level.eps, bburx=540, bbury=720, bbllx=0, bblly=200, height=7.0in,width=6.2in}
  \hbox{\hspace*{-0.5in}\epsfxsize=7.0in\epsffile{plots/top_level.eps}
	}
\end{center}
\vspace*{-1.7in}

\caption{Top Level Diagram for DIRAC}
\label{top level}          
\end{figure}

\clearpage

\begin{figure}[p]
\begin{center}
% \epsfig{figure=plots/tower.eps}%, bburx=540, bbury=720, bbllx=0, bblly=200,height=7.0in,width=6.2in}
  \hbox{\hspace{-0.5in}
	\epsfxsize=7in\epsffile{plots/tower.eps}
	}
\end{center}
\vspace*{-1.7in}
\caption{Tower Modules --- 6 on each DIRAC Board}
\label{tower}
\end{figure}

\clearpage

\subsection{Global CDF Control Signals}

All global\footnote{Global refers to all CDF Trigger and DAQ control
signals.} control signals are routed along P2 from the Tracer module
in slot 2.\cite{tracer} The following is an incomplete list of CDF
reserved signals on the outer rows of P2.  This list contains only
those signals used by DIRAC.
\begin{itemize}
\item {\bf CDF\_L1A*}    --- Global L1 Accept
\item {\bf CDF\_L1R*}    --- Global L1 Reject
\item {\bf CDF\_B0*}     --- Bunch Zero
\item {\bf CDF\_CLK}     --- Differential PECL Clock Signal (132 ns)
\item {\bf CDF\_RESET*}  --- Master Reset
\item {\bf CDF\_L1BA0*}  --- L1 Buffer Address Bit 0
\item {\bf CDF\_L1BA1*}  --- L1 Buffer Address Bit 1
\item {\bf CDF\_HALT*}   --- Stop Processing Events
\item {\bf CDF\_ERROR*}  --- Tell the Trigger Supervisor Interface (TSI) 
that an Error occurred on DIRAC
\end{itemize}
Two other signals are relavent to DIRAC but not used directly.
\begin{itemize}
\item {\bf CDF\_L2A*}    --- Global L2 Accept
\item {\bf CDF\_L2R*}    --- Global L2 Reject
\end{itemize}
{\bf CDF\_L1A*}, {\bf CDF\_L1R*}, {\bf CDF\_L2A*} and {\bf CDF\_L2R*}
are the global trigger decisions from the Trigger Supervisor Interface
(TSI).\cite{TSI 1}\cite{TSI 2} With a {\bf CDF\_L1A*} the TSI sends
{\bf CDF\_L1B0*} and {\bf CDF\_L1B1*} designating in which of 4
buffers to store the event while waiting for a L2 decision.  On a {\bf
CDF\_L2A*}, the VME Readout Controller (VRC) in every crate will
readout the appropriate L2 buffer via VME.  On a {\bf CDF\_L2R*},
nothing is done on DIRAC, the buffer in question is merely available
for another event.  The TSI keeps track of the status of the buffers.
The {\bf CDF\_CLK} signal has a period of 132 ns, regardless of the
actual bunch spacing.  The {\bf CDF\_RESET*} signal, generated by the
TSI, tells DIRAC to reset its FIFOs.  {\bf CDF\_RESET*} serves two
purposes: 1) a method to re--synchronize the system without stopping
the run and 2) initiating a run.\cite{Timing Doc} The {\bf
CDF\_ERROR*} signal tells TSI that an error occurred on DIRAC.  An
error for the DIRAC board is sent only if one of the FIFOs on DIRAC
becomes full.  This could indicate either a loss of sync or a clock
signal that did not get properly distributed on DIRAC.

\subsection{\bf VME\_Interface}

The {\bf VME\_Interface} allows DIRAC to communicate with other cards
in a VME crate as a slave only using A32/D32/D32(BLT) protocol defined
by the VME standard.\cite{VME standard} As specified in the VME64-P
standard, Dirac recognizes only addresses corresponding to its slot
number.  For more information about the DIRAC VME interface please
refer to appendix A.

\subsection{Custom\_P3 and The TowLat Chip}
\label{section-towlat}

The 20 bits of energy in each tower come through the {\bf CUSTOM\_P3}
module.  The energies arrive at DIRAC as transverse energy and with
the proper pedastal already subtracted.  These 20 bits are divided
into 10 bits of hadron transverse Energy (E$_{T}$) and 10 bits of
electromagnetic E$_T$.  One count corresponds to $0.125 \egev$ for a
full scale of $127.875 \egev$.  These signals are grouped into a 120
bit bus called {\bf TOWIN(119:0)}.  This bus is fanned out in six 20
bit segments and routed to the {\bf TOWLAT} section within the {\bf
Towers} module.(see Figure \ref{tower})

The {\bf TOWLAT} section contains 6 EPLDs.  These chips latch the
input energies at a time t$_{\mbox{Calorimetry}}$.  Each chip
represents one trigger tower, receiving 10 bits of hadron and 10 bits
of electromagnetic data.  The functionality of the Tower Latch chip is
fully described in a separate document.\cite{Dirac Detailed} The
ability to mask off any individual section of a tower is provided.
The masked towers will contribute 0 energy to the sum for that tower
and will output a value of 0 to all other outputs.  The two 10-bit
energies are echoed (after masking and latching) to the {\bf
FTOWERS(119:0)} bus.  The {\bf FTOWERS(119:0)} bus is then sent to the
Level 2(L2) DCAS boards (described later).\cite{DCAS} Eight of the 10
electromagnetic energy bits are used in later L1 trigger decisions.
These 8 bits are bundled into the {\bf TOWEM(47:0)} bus.  The choice
of which 8 bits are used is determined by the state the Tower
Granularity bit in the control registers.   One can either choose to
have $0.250\egev$ or $0.500\egev$ resolution on both the {\bf TOWEM}
and {\bf TOWTOT} energies.
%\footnote{(3/16/05) It is reported that the resolution selection does not work and has not so far during Run~2.  The value is fixed at $0.500\egev$.}  
Finally a crude measure of the hadron
energy is provided by {\bf LSBHAD(17:0)}.  This bus contains 3 bits
per trigger tower that are either the 3 least significant bits (LSBs)
or the next to 3 LSBs.  The choice is made via a bit in the control
registers.  These bits are used to make a rough cut on hadron energy
in a tower for electron triggers.  The two 10-bit data words input to
the {\bf TOWLAT} section are summed to produce an 8-bit number that is
the total energy in each trigger tower.  In the event of an overflow
in the sum, all bits are turned on, i.e. the energy is set to
full--scale.  The default resolution of the summed energy is $0.250
\egev$ with a full scale of $63.75 \egev$, as mentioned earlier the
resolution can be changed.  The bus {\bf TOWTOT(47:0)} is the
collection of all 6 chips total energies.

Note that if one uses a granularity of 0.250 GeV (0.500 GeV) here in
the {\bf TOWLAT} section, to form the Dirac decision, then for the
ETSUM section, the granularity of the 8 bit ETSUM word sent to
CrateSum is 0.500 GeV (1.000 GeV), respectively. This change was done
recently, anticipating that the (previous) full range on ETSUM still
would not be comfortable for Level 2. This change was done on the
EtInp chips, U31, U33, U34, program bigadder.gdf~\footnote{These chips
can be reprogrammed, if needed.}.

\subsection{Alignment Fifo}

The {\bf TOWTOT(47:0)}, {\bf TOWEM(47:0)} and {\bf LSBHAD(17:0)} buses
are fed to the {\bf AL\_FIFO} section for time aligning with the
tracking trigger bits.  The purpose of this FIFO is to make sure that
the tracking information and the tower energy bits being examined are
from the same event.  For example, two parts of one event can get out
of time because the tower energy is processed faster than the tracking
information.  This FIFO prevents such an occurence, by waiting a time
t$_{\mbox{Tracking}}$ after the bunch crossing to release the event
for further processing.  The outputs of this section are called {\bf
TOTOUT(47:0)}, {\bf EMOUT(47:0)} and {\bf LSBOUT(17:0)} and are sent
to the {\bf Decision} section.

\subsection{Decisions, Decisions\dots}

The {\bf Decision} section receives the outputs of the {\bf AL\_FIFO}
section.  In addition, {\bf Decision} accepts an 18 bit bus, called
{\bf TR(17:0)} from the {\bf Track} section.  Twelve (EM + TOT) SRAMs
receive these 4 busses and make the trigger decision.  For each
trigger tower, one SRAM looks at the {\bf TOWTOT} and {\bf TR} busses
and generates the 8 jet trigger decisions.  The other SRAM examines
the {\bf TOWEM}, {\bf LSBHAD} and {\bf TR} busses and makes the 8
electromagnetic trigger decisions.  These decisions are combined into
the {\bf CSUM(95:0)} bus.  Note: There are 16 decisions per trigger
tower for a total of 96 bits.  However, there are only 13(ten 1--bit
and three 2--bit) L1 triggers available for the global decision.  The
reduction from 16 to 13 is performed in the {\bf CSUM} section.  The
{\bf CSUM} bus is sent to two modules {\bf CardSum} and {\bf DAQ}.

A brief discussion of the physics behind the {\bf Decision} section is
in order.  The jet decisions are based on the total energy in a given
trigger tower.  In addition, the existence of a track above a
threshold is available on an individual tower basis.  This allows, for
the first time at CDF, the existence of a true jet trigger at L1.  The
electromagnetic decision is equally revolutionary.  The
electromagnetic (EM) decision is based on the amount of EM energy in
the tower, the existence of a track pointing to a given trigger tower
and the amount of hadronic energy in the tower.  The crude hadronic
energy information allows either a factor of 8 or 16 cut on Em/Had at
level 1.  The {\bf LSBHAD} data is 3 bits from the hadronic energy for
the tower.  As described earlier it is either the 3 LSBs or the next
to 3 LSBs, thus providing a measure of the amount of hadronic energy
with a maximum of either $\frac{7}{8} \egev$ or $1\frac{3}{4} \egev$
and resolution of $0.125$ or $0.25 \egev$, respectively (again a
programmable parameter).  The basic jet and electron triggers are easy
to envision.  A new interesting trigger for level 1 calorimetry may be
for muons.  One can cut on a window of energy (minimum ionizing)
around a few GeV and ask for a track pointing at this tower.  This
combined with the normal muon triggers available is likely to give an
even stronger handle on muon triggering at level 1.

\subsection{Data Acquisition (DAQ)}

{\bf DAQ} stores the event while waiting for a L2 decision.  This
section contains a L1 FIFO and a set of 4 L2 buffers for each set of
8 trigger decisions.  The L1 FIFO is 256 deep, easily accomadating
the maximum L1 decision time of 42 crossings (42 $\times$ 132 ns =
5.544 $\mu$s).  If a {\bf CDF\_L1R*} is received by Dirac, the next
event in the L1 FIFO is strobed and ignored.  If a {\bf CDF\_L1A*}
is received, the next event is strobed out of the L1 FIFO and read
into one of the 4 L2 buffers based on the state of {\bf CDF\_L1BA0*}
and {\bf CDF\_L1BA1*}.  If a Level 2 reject is issued, nothing is
done in the crate.  The buffer corresponding to this event is marked
as open by the TSI.\cite{TSI 1}\cite{TSI 2} If a Level 2 accept is
issued, the VRC contained in each crate accesses the appropriate L2
buffer via VME.  The L2 buffers on Dirac are placed at the proper
place in the memory map for access during readout by the VRC and
TRACER.\cite{CDF BP}

\subsection{DIRAC to L2 connection}

The module {\bf Front\_Panel} takes {\bf FTOWERS(119:0)} and sends
the 120 signals to the L2 DCAS boards via front panel
connectors.\cite{DCAS} The signals are sent differentially, requiring
240 pins.  This is done through three 80 pin Honda connectors located on
the front panel (FP1, FP2, FP3).  Tables \ref{fp1}, \ref{fp2} and
\ref{fp3} show the pin assignments for these connectors, the number
listed next to E$_{\mbox{T}}$ is the bit number in {\bf FTOW}. (Note that facing the connector in the board, pin 1 is the lower one and pin 40 the upper one). At
time t$_{\mbox{Calorimetry}} + 37$ns after the bunch crossing, the
tower E$_{\mbox{T}}$ information is valid on the cable to DCAS.

\begin{table}
\centering
\caption{Front Panel Connector 1 -- FP1}
\label{fp1}
$$
\begin{array}{|c||c|c|} \cline{2-3}
\multicolumn{1}{c}{}  & \multicolumn{2}{|c|}{\mbox{Column}} \\ \hline
\mbox{Row} & \mbox{A} & \mbox{B} \\ \hline \hline
1 & \mbox{EM Tow 0 E}_{\mbox{T}}\mbox{0} & 
    \mbox{EM Tow 1 E}_{\mbox{T}}\mbox{0}\\ \hline
2 & \mbox{EM Tow 0 E}_{\mbox{T}}\mbox{1*} & 
    \mbox{EM Tow 1 E}_{\mbox{T}}\mbox{1*}\\ \hline
3 & \mbox{EM Tow 0 E}_{\mbox{T}}\mbox{2} & 
    \mbox{EM Tow 1 E}_{\mbox{T}}\mbox{2}\\ \hline
\vdots & \multicolumn{2}{|c|}{\vdots} \\ \hline
38 & \mbox{HAD Tow 0 E}_{\mbox{T}}\mbox{8*} & 
     \mbox{HAD Tow 1 E}_{\mbox{T}}\mbox{8*}\\ \hline
39 & \mbox{HAD Tow 0 E}_{\mbox{T}}\mbox{9} & 
     \mbox{HAD Tow 1 E}_{\mbox{T}}\mbox{9}\\ \hline
40 & \mbox{HAD Tow 0 E}_{\mbox{T}}\mbox{9*} & 
     \mbox{HAD Tow 1 E}_{\mbox{T}}\mbox{9*}\\ \hline
\end{array}
$$
\end{table}

\clearpage

\begin{table}
\centering
\caption{Front Panel Connector 2 -- FP2}
\label{fp2}
$$
\begin{array}{|c||c|c|} \cline{2-3}
\multicolumn{1}{c}{}  & \multicolumn{2}{|c|}{\mbox{Column}} \\ \hline
\mbox{Row} & \mbox{A} & \mbox{B} \\ \hline \hline
1 & \mbox{EM Tow 2 E}_{\mbox{T}}\mbox{0} & 
    \mbox{EM Tow 3 E}_{\mbox{T}}\mbox{0}\\ \hline
2 & \mbox{EM Tow 2 E}_{\mbox{T}}\mbox{1*} & 
    \mbox{EM Tow 3 E}_{\mbox{T}}\mbox{1*}\\ \hline
3 & \mbox{EM Tow 2 E}_{\mbox{T}}\mbox{2} & 
    \mbox{EM Tow 3 E}_{\mbox{T}}\mbox{2}\\ \hline
\vdots & \multicolumn{2}{|c|}{\vdots} \\ \hline
38 & \mbox{HAD Tow 2 E}_{\mbox{T}}\mbox{8*} & 
     \mbox{HAD Tow 3 E}_{\mbox{T}}\mbox{8*}\\ \hline
39 & \mbox{HAD Tow 2 E}_{\mbox{T}}\mbox{9} & 
     \mbox{HAD Tow 3 E}_{\mbox{T}}\mbox{9}\\ \hline
40 & \mbox{HAD Tow 2 E}_{\mbox{T}}\mbox{9*} & 
     \mbox{HAD Tow 3 E}_{\mbox{T}}\mbox{9*}\\ \hline
\end{array}
$$
\end{table}

\clearpage

\begin{table}
\centering
\caption{Front Panel Connector 3 -- FP3}
\label{fp3}
$$
\begin{array}{|c||c|c|} \cline{2-3}
\multicolumn{1}{c}{}  & \multicolumn{2}{|c|}{\mbox{Column}} \\ \hline
\mbox{Row} & \mbox{A} & \mbox{B} \\ \hline \hline
1 & \mbox{EM Tow 4 E}_{\mbox{T}}\mbox{0} & 
    \mbox{EM Tow 5 E}_{\mbox{T}}\mbox{0}\\ \hline
2 & \mbox{EM Tow 4 E}_{\mbox{T}}\mbox{1*} & 
    \mbox{EM Tow 5 E}_{\mbox{T}}\mbox{1*}\\ \hline
3 & \mbox{EM Tow 4 E}_{\mbox{T}}\mbox{2} & 
    \mbox{EM Tow 5 E}_{\mbox{T}}\mbox{2}\\ \hline
\vdots & \multicolumn{2}{|c|}{\vdots} \\ \hline
38 & \mbox{HAD Tow 4 E}_{\mbox{T}}\mbox{8*} & 
     \mbox{HAD Tow 5 E}_{\mbox{T}}\mbox{8*}\\ \hline
39 & \mbox{HAD Tow 4 E}_{\mbox{T}}\mbox{9} & 
     \mbox{HAD Tow 5 E}_{\mbox{T}}\mbox{9}\\ \hline
40 & \mbox{HAD Tow 4 E}_{\mbox{T}}\mbox{9*} & 
     \mbox{HAD Tow 5 E}_{\mbox{T}}\mbox{9*}\\ \hline
\end{array}
$$
\end{table}

\clearpage

\subsection{Tracking Information}

As discussed earlier, XTRP sends 8 differential bits representing
tracks found by the XFT in the 15$^{\circ}$ wedge covered by each
DIRAC board.  These differential signals are received by {\bf
Front\_Panel} through front panel connector 4 (FP4).  {\bf Front
Panel} then outputs the 8 single ended signals as {\bf TRACKIN(7:0)}.
{\bf TRACKIN} is latched at time t$_{\mbox{Tracking}}$ after the bunch
crossing by the module {\bf TRACK}.  The module {\bf TRACK} contains
three 256$\times$8 SRAMs that take in the 8 bits as an address and
output which trigger towers pass each tracking trigger on the {\bf
TR(17:0)} bus.  Since SRAMs are used for the tracking bits and in the
{\bf Decision} section, the final decision can be an arbitrary
combination of the 8 tracking bits and the energy bits.  This allows
for a change in meaning of the 8 tracking bits.  The mapping is
downloaded at the beginning of each run.

\subsection{Trigger Summary}

The module {\bf CardSum} accepts the 8+8(EM+Jet) trigger bits from
each of the 6 towers on the {\bf CSUM(95:0)} bus.  This module
consists of 5 Erasable Programmable Logic Devices (EPLD).  The 96 bits
are sent to 4 EPLDs which produce 2 bits output for each trigger type,
for a total of 32 bits.  There are 16 different triggers at this
summary stage, 8 2--bit jet and 8 2--bit EM triggers.  Each trigger
summary tells whether 0, 1 , 2 or greater than 2 towers passed each
trigger type.  For trigger 0, bits 0 and 1 tell how many of the 6
towers passed that trigger, bits 2 and 3 tell how many passed trigger
1, etc\ldots.  Table \ref{csum} shows the meaning of each set of two
bits.

These 32 bits are then sent to the CSUM\_MUX EPLD.  This chip takes
the 8+8 2--bit triggers and passes 10 1--bit and 3 2--bit triggers to
the CardSum backplane drivers. The CSUM\_MUX Internal register in the
memory map determines which of the 8+8 triggers are used.  In the
current configuration, the first 10 bits sent over the backplane to
CrateSum(CS) are the 10 1--bit triggers and the next 6 bits are the 3
2--bit triggers, for a total of 16 bits, {\bf CSUMOUT(15:0)}.  The
CSUM\_MUX internal register is a 17--bit register and table \ref{CSUM
MUX} shows how the individual bits are multiplexed.  Each 1--bit
trigger now tells whether 0 trigger towers pass or at least one
trigger tower passed the particular trigger.  Some explanation for
table \ref{CSUM MUX} is neccessary.  The first column represents the
CSUM\_MUX internal register bit.  The second column shows which input
is used for the On state of the bit from column 1.  The third column
is the same but for the Off state of the bit.  Column four shows which
of the 16 output lines, {\bf CSUMOUT}, is driven by the selected
input.  There are two sets of triggers that are a selection out of 8
triggers to drive one output line.  These are shown as a combination
of columns 2 and 3 where the phrase ``select xx'' is used.  This means
that the triggers xx are selected based on the state of the 3 bits(an
8-1 multiplexer). If 000 (binary) is written to CSUM Register bits 8-10, then trigger Jet0 is 
selected on TRSUM bit8. If 011, then trigger Jet3. If 111, trigger EM3.

The 16--bit trigger summary word, {\bf TRSUM(15:0)}, is driven on the
backplane at t$_{\mbox{Tracking}}+215$ns after the bunch crossing, since tracking data arrives
after Calorimeter Data. {\bf TRSUM(15:0)} remains valid there for 1 clock cycle after that.   {\bf
TRSUM} is sent to {\bf Custom\_P3} and out over the P3 backplane to
CS.  A minor timing requirement should be noted at this time.  {\bf
TRSUM} has 49ns (2*132ns-215ns) to traverse the backplane and be
latched by CS.  The backplane propagation time should be under 5ns,
leaving CS with 45ns to latch the data.  This is easily accomplished
with current technology.

\begin{table}
\centering
\caption{Meaning of the 2 Bits Representing How Many Towers Passes a Trigger}
\label{csum}
$$
\begin{array}{||c|c||c||} \hline
\multicolumn{2}{||c||}{\mbox{Bit}} & \mbox{How Many} \\ \cline{1-2}
1 & 0 & \mbox{Towers Passed}\\ \hline \hline
0 & 0 & 0 \\ \hline
0 & 1 & 1 \\ \hline
1 & 0 & 2 \\ \hline
1 & 1 & > 2 \\ \hline
\end{array}
$$
\end{table}

\clearpage

\begin{table}
\centering
\caption{Interpretation of the CSUM\_MUX Register}
\label{CSUM MUX}
$$
\begin{array}{||c||c|c||c||} \hline
\mbox{\bf CSUM} & \multicolumn{2}{|c||}{\mbox{Bit State}} & \mbox{{\bf TRSUM} Bit} \\ \cline{2-3}
\mbox{Register Bit} & \mbox{On} & \mbox{Off} & \mbox{Driven}\\ \hline \hline
0 & \mbox{Jet 0} & \mbox{EM 0} & 0 \\ \hline
1 & \mbox{Jet 1} & \mbox{EM 1} & 1 \\ \hline
2 & \mbox{Jet 2} & \mbox{EM 2} & 2 \\ \hline
3 & \mbox{Jet 3} & \mbox{EM 3} & 3 \\ \hline
4 & \mbox{Jet 4} & \mbox{EM 4} & 4 \\ \hline
5 & \mbox{Jet 5} & \mbox{EM 5} & 5 \\ \hline
6 & \mbox{Jet 6} & \mbox{EM 6} & 6 \\ \hline
7 & \mbox{Jet 7} & \mbox{EM 7} & 7 \\ \hline
8-10 & \multicolumn{2}{|c||}{\mbox{Select EM 0-3, Jet 0-3}} & 8 \\ \hline
11-13 & \multicolumn{2}{|c||}{\mbox{Select EM 4-7, Jet 4-7}} & 9 \\ \hline
14 & \mbox{Jet 5} & \mbox{EM 5} & 10-11 \\ \hline
15 & \mbox{Jet 6} & \mbox{EM 6} & 12-13 \\ \hline
16 & \mbox{Jet 7} & \mbox{EM 7} & 14-15 \\ \hline
\end{array}
$$
\end{table}

\clearpage

\subsection{Sum E$_{\mbox{T}}$}

{\bf EtSum} accepts {\bf TOWTOT(47:0)} and adds the six 8 bit tower
E$_{\mbox{T}}$s into one 8 bit E$_{\mbox{T}}$.  This sum represents
the total energy deposited in all 12 towers.  If TOW\_GRAN bit of Control1 is OFF, then if 
$\Sigma$E$_{\mbox{T}}$ is greater than $128 \egev$ (8 bits with a
resolution of $0.5 \egev$), then all 8 bits are asserted to
represent an overflow.\footnote{The version of the summing firmware currently available (and used so far during the run) does not carry forward the saturation of a single tower through the summing (3/16/05 PJW).}  If TOW\_GRAN bit of Control1 is ON, then if 
$\Sigma$E$_{\mbox{T}}$ is greater than $256 \egev$ (8 bits with a
resolution of $1 \egev$), then all 8 bits are asserted to
represent an overflow.
	Again, the meaning of the 8 bits sent to Cratesum depends on the TOW\_GRAN bit of Control\_1:

If TOW\_GRAN is ON, the default choice, the 8 bits have a full scale of 256 GeV, resolution of 1 GeV.

If TOW\_GRAN is OFF, the 8 bits have a full scale of 128 GeV, resolution of .5 GeV.
 

Four EPLDs are used to perform this summing
in a bi-level process.  The 3 EtInp chips sum 2 towers each and
apply a threshold to all towers. The input energies into these chips have a LSB of 
0.5 (0.25) GeV, for TOW\_GRAN ON(OFF).
  This threshold is 0, 1, 2 or 3 bit
shifts as defined in the 2--bit ET\_THRESH register in Control register 1.  For
example, if the threshold is set to 2 bits, then any tower with
energy below the 2nd bit($<$4 counts) is not included in the sum.
This would represent a threshold of $4 \times 0.5~\footnote{Again depending on the TOW\_GRAN bit. This case is for a granularity of 0.50 GeV, bit ON.} \egev = 2 \egev$. This way one can correct for pedestals of 0, .5, 1 or 2 $\egev$.  Table~\ref{Sum Threshold} lists the possible tower thresholds for the two possible values of tower granularity.  
The output of these chips into the EtOut chip is shifted up by one, for a LSB of 1 (0.5) GeV, for TOW\_GRAN ON(OFF).
The EtOut chip sums the outputs of the EtInp chips into the final
8--bit number.  Again, the final output into CrateSum will have a LSB of  1 (0.5) GeV, for TOW\_GRAN ON(OFF).
{\bf ETSUM} is latched
t$_{\mbox{Calorimetry}}+264$ns after the bunch crossing by the
backplane latch.  {\bf ETSUM} passes through {\bf Custom\_P3} and is
valid on the backplane 14ns later, leaving 132ns-14ns=118ns to
traverse the backplane and get latched on CS.  Table~{Sum Granularity} summarizes the granularity and full scale vales for each stage of the Sum E$_{\mbox{T}}$\ calculation for the two possible values of the tower granularity.  The ranges for Cratesum and PreFRED are included for convenience of the reader.

Again, read the important note at the end of section \ref{section-towlat}.

\begin{table}
\centering
\caption{Tower Thresholds (ET\_THRESH) for Sum E$_{\mbox{T}}$\ Calculation}
\label{Sum Threshold}
$$
\begin{array}{|c|c||c|c|} \cline{3-4}

\multicolumn{2}{c}{}  & \multicolumn{2}{|c|}{\mbox{Granularity (GeV)}} \\ \cline{3-4}
\multicolumn{2}{c|}{}  & \mbox{0.25}  & \mbox{0.50} \\ \cline{3-4}
\multicolumn{2}{c}{}  & \multicolumn{2}{|c|}{\mbox{TOW\_GRAN (Control 1)}} \\ \cline{3-4}
\multicolumn{2}{c|}{}  & \mbox{0}  & \mbox{1} \\ \hline
\multicolumn{2}{|c||}{\mbox{bit}}  & \multicolumn{2}{c|}{} \\ \hline

1 & 0 & \multicolumn{2}{|c|}{\mbox{$E_T$(GeV)$\geq$}}  \\ \hline \hline
0 & 0 &  \mbox{0.0}  & \mbox{0.0} \\ \hline
0 & 1 &  ~~~~~~0.5~~~~~~  & ~~~~~1.0~~~~~ \\ \hline
1 & 0 &  1.0  & 2.0 \\ \hline
1 & 1 &  2.0  & 4.0 \\ \hline

\end{array}
$$
\end{table}


\begin{table}
\centering
\caption{Granularity and Full scale (in GeV) for stages of Sum E$_{\mbox{T}}$\ Calculation}
\label{Sum Granularity}
$$
\begin{array}{|c|c||c|c||c|c|} \cline{3-6}

\multicolumn{2}{c}{}   & \multicolumn{4}{|c|}{\mbox{Granularity (GeV)}} \\ \cline{3-6}
\multicolumn{2}{c}{}   & \multicolumn{2}{|c||}{\mbox{0.25}}  & \multicolumn{2}{|c|}{\mbox{0.50}} \\ \cline{3-6}
\multicolumn{2}{c}{}   & \multicolumn{4}{|c|}{\mbox{TOW\_GRAN (Control 1)}} \\ \cline{3-6}
\multicolumn{2}{c}{}   & \multicolumn{2}{|c||}{\mbox{0}}  & \multicolumn{2}{|c|}{\mbox{1}} \\ \cline{2-6}

\multicolumn{1}{c|}{}  & \mbox{Bits} & \mbox{lsb}  & \mbox{FS}  & \mbox{lsb}  & \mbox{FS} \\ \cline{2-6} \hline

\mbox{DIRAC Input}        & 10 & 0.125 & 127.875 & 0.125  & 127.875 \\ \hline 
\mbox{Tower Sum (TOWTOT)} & 8  & 0.25  & 63.75   & 0.50   & 127.5 \\ \hline 
\mbox{Two Tower (ETINP)}  & 8  & 0.50  & 127.50  & 1.00   & 255.0 \\ \hline 
\mbox{Six Tower (ETINP)}  & 8  & 0.50  & 127.50  & 1.00   & 255.0 \\ \hline \hline
\mbox{Wedge Sum (Cratesum)} & 10  & 0.50  & 511.50  & 1.00   & 1023.0 \\  \hline \hline
\mbox{$\mathrm{SUM~E_T}$ (PreFRED)} & 11  & 1.0  & 2047.0  & 2.0   & 4094.0 \\  \hline 
\mbox{$\mathrm{E_{Tx}/E_{Ty}}$ (PreFRED)} & 10  & 1.0  & 1023.0  & 2.0   & 2046.0 \\  \hline 
\mbox{$\mathrm{ {\not\! E}_T}^2$ GeV$^2$\ (PreFRED)} & 16  & (1.0)^2  & (255.0)^2  & (2.0)^2   & (511.0)^2 \\  \hline 

\end{array}
$$
\end{table}


\subsection{In System Programmability}

The ability to reprogram the functionality on a board of sufficient
complexity is a must for a system to endure over a long period of
time.  We provide this functionality by allowing most of the EPLDs to
be reprogrammed through the Bit Blaster (or Byte Blaster~\footnote{Altera's Byte Blaster can (and was) also be used to 
program the chain. It's MUCH faster then the Bit Blaster.}) interface.~\cite{altera
BB}~\footnote{The EtOut and Csum chips are not re-programmable, but
they contain only simple summing logic.}  The {\bf ISP} section
contains the 10--pin Bit Blaster connecter on the front panel.  This
interface is a serial line strung through all chips in the chain.
There are 4 signals, TDI, TDO, TMS and TCK involved in the ISP
protocol.
\begin{itemize}
\item TDI - Test Data In, is the input data
\item TDO - Test Data Out, is the output data(input to next chip)
\item TMS - Test Mode Select
\item TCK - Test Clock, is the clock to strobe data through the chain
\end{itemize}
Two busses are routed through many sections of the schematics, {\bf
ISP\_IN(2:0)} and {\bf ISP\_OUT(2:0)}.  {\bf ISP\_IN} is always the
input lines to the chip(TDI, TMS, TCK).  Likewise {\bf ISP\_OUT} are
the outputs of the chip.  The outputs of one chip are tied to the
inputs of the next chip, hence the serial chain.  Bits 1 and 2(TMS and
TCK) are tied together for the whole board.  Bit 0 is TDI for input
and TDO for output.  The programming chain is shown in the upper right
corner of figure \ref{top level}.

\section{Addressing}

Throughout the rest of the paper, the C language numerical base
identification standard is used.  Any number prefixed by ``0x'' is a
hexidecimal number.  Any number without a prefix is decimal.

Figure \ref{address space} shows the division of VME address space for
DIRAC.  Each DIRAC card uses a 16 Mbyte slice from the ``Defined
space'' section.  Bits A23:A02 address DIRAC's internal memory.
A23:A20 are decoded into 16 ``Block''s of memory.  Each ``Block'' is
256K 32--bit(Quad) words addressed sequentially by A19:A02.  Block
transfers are limited by VME specification IEEE 1014--1987 to 256
bytes(64 Quad words) and performed by incrementing, with every data
strobe, A07:A02 from a pre--loaded base address on DIRAC.  In
hexadecimal, a full 32--bit address looks like {\bf YYZAAAAA}, where
\begin{itemize}
\item {\bf YY} --- A31:A24 = $<$GA4:GA0$>$000 --- Zone selector.  32
Zones in the address space.  This selects a slot in the crate,
$<$GA4:GA0$>$.
\item {\bf Z} --- A23:A20 --- ``Block'' selector.  16 ``Blocks'' on
DIRAC.
\item {\bf AAAAA} --- A19:A00 --- Word selector.  256K Quad words per
``Block''.
\end{itemize}

\begin{figure}[p]
\begin{center}
% \epsfig{figure=plots/address_space.eps, width=6.2in}
  \hbox{\hspace*{-0.5in}\epsfxsize=7in\epsffile{plots/address_space.eps}}
\end{center}
\caption{VME Address Space}
\label{address space}
\end{figure}

\clearpage

\subsection{DIRAC MLUs}

There are numerous Memory Look Ups(MLUs) on DIRAC.  The location of
the MLUs in DIRAC address space is specified in table \ref{DIRAC mlu}.
MLU\_T\_T refers to SRAMs in the {\bf Decision} section and
TR\_FAN\_OUT to SRAMs in the {\bf Track} section.  Each of these SRAMs
must be downloaded at the beginning of every run with trigger
decisions or tracking fan out information.  Each address is readable
for diagnostics.  Writing to the memory is only allowed when in {\bf
LOAD} mode, and bits 6 and 7 of CONTROL1 are OFF (0).({\bf LOAD} mode is described later in this document)

\begin{table}
\centering
\caption{DIRAC Memory Look--Up Units}
\label{DIRAC mlu}
$$
\begin{array}{||c||c|c|c|c|c||} \hline
\mbox{Memory} & \mbox{Towers} & \mbox{Size} & \mbox{``Block''} & 
	\mbox{Addresses(A23:A00)} & \mbox{R/W} \\ \hline \hline
\mbox{MLU\_T\_T} & 0\mbox{--}1 & 32\mbox{K} \times 32 & 4 & 
	0\mbox{x}4\mbox{1FFFC}:0\mbox{x}400000 & \mbox{RW} \\ \hline
\mbox{MLU\_T\_T} & 2\mbox{--}3 & 32\mbox{K} \times 32 & 5 & 
	0\mbox{x}5\mbox{1FFFC}:0\mbox{x}500000 & \mbox{RW} \\ \hline
\mbox{MLU\_T\_T} & 4\mbox{--}5 & 32\mbox{K} \times 32 & 6 & 
	0\mbox{x}6\mbox{1FFFC}:0\mbox{x}600000 & \mbox{RW} \\ \hline
\mbox{TR\_FAN\_OUT} & \mbox{all} & 256 \times 24 & 3 & 
	0\mbox{x}3003\mbox{FC}:0\mbox{x}300000 & \mbox{RW} \\ \hline
\end{array}
$$
\end{table}

\clearpage

The final decisions for which triggers pass given a tower energy
threshold and tracking configuration is loaded into the MLU\_T\_T
SRAMs.  These are 6 towers $\times$ 2 types (HAD\&EM) $\times$ 32K
$\times$ 8 bits and organized as three 32K $\times$ 32 bits sections.
Special note: Bits 8:15 and 24:31 of each section really only occupy
4K independent addresses.  This is because the jet MLUs do not require
the extra 3 bits for {\bf LSB\_HAD} and the contents must be the same
for all values of these 3 bits.  Hence the factor of 8.  Therefore,
when downloading the memories, care must be taken to repeat the 4K
data for the whole 16K section of memory otherwise invalid data would
be downloaded to the Jet MLUs.  For Example, if you want to download
0x55 to tower 0(EM) and 0x45 to tower 1(Jet) for location 0x0 within
the memory, you would write 0x4555 to location 0x400000.  Now you move
along and want to write 0x66 to location 0x402000, so you write 0x4566
to location 0x402000.  Thus you overwrite the location in the Jet SRAM
with the same value.  If you were to write 0x0066 to location
0x402000, you would overwrite the Jet MLU with 0x00.

The mapping information for tracking triggers is loaded into the
TR\_FAN\_OUT SRAMs.  This memory is 6 towers $\times$ 256 $\times$ 4
bits and is organized as a 256 $\times$ 24 bits space within ``Block''
3.  This mapping depends explicitly on the meaning of the bits coming
from the XTRP boards.  This is programmable on the XTRP board and here
as well.

\subsection{DIRAC DAQ Memory}

According to the CDF specification for readout, the first long word of
every DAQ readout specifies the origination and bunch number for the
event data.\cite{first DAQ word spec} This word consists of the 19 bits (the MSBits) specifying the board type, 5--bit
geographical address, 
and 8 bits (the LSBits) for
the bunch number.\cite{first DAQ word spec} Dirac follows this word
with 3 long words of data containing the 16 trigger decisions for all
6 towers.  The second readout word contains the trigger decisions for
towers 0 and 1.  The word is divided into 4 8 bit words (from LSB to
MSB) containing the EM then HAD decisions for tower 0 followed by
tower 1 in the same order.  The remaining two words contain the
information for towers 2--3 and towers 4--5, in the same
configuration.  This memory is divided into 4 distinct sections, one
for each L2 buffer.  As per the CDF specification, the locations of
these buffers are shown in table \ref{daq memory}.\cite{CDF BP} During
DAQ readout the buffer containing the L2 event is accessed using
D32(BLT) (Note: this is only 4 long words in length)
\begin{table}.
\centering
\caption{DIRAC DAQ Memory}
\label{daq memory}
$$
\begin{array}{||c||c|c|c|c||} \hline
\mbox{DAQ Buffer} & \mbox{Size} & \mbox{``Block''} & 
	\mbox{Addresses(A23:A00)} & \mbox{R/W} \\ \hline \hline
0 & 4 \times 32 & 8 & 0\mbox{x}80000\mbox{C}:0\mbox{x}800000 
	& \mbox{RO} \\ \hline
1 & 4 \times 32 & 9 & 0\mbox{x}90000\mbox{C}:0\mbox{x}900000 
	& \mbox{RO} \\ \hline
2 & 4 \times 32 & \mbox{A} & 0\mbox{xA0000C}:0\mbox{xA}00000 
	& \mbox{RO} \\ \hline
3 & 4 \times 32 & \mbox{B} & 0\mbox{xB0000C}:0\mbox{xB}00000 
	& \mbox{RO} \\ \hline
\end{array}
$$
\end{table}

\clearpage

\subsection{Data Path Access}

These sections of VME memory are used to test the functionality of
DIRAC.  It allows access to virtually all points along the data path.
The tests themselves are beyond the scope of this paper, but a
description of the part on the board that the memory effects is given
below.  In {\bf LOAD} mode, data path access is unlimited and any
operation can be performed.  For example, we can load all the towers
with some energies and propagate the data through Dirac.  In {\bf RUN}
mode, access is limited to reading from the data path only (spying).
DIRAC will not allow you to write data that might interfere with
normal data taking.

Table \ref{tower data path} summarizes the memory allocation for data
path access to the Tower Latches.  Table \ref{other data path}
describes the memory map for all other data path access.
\begin{table}
\centering
\caption{Tower Latch Data Path Access Map}
\label{tower data path}
$$
\begin{array}{||c||c|c|c|c|c|c||} \hline
\mbox{Memory} & \mbox{Towers} & \mbox{Size} & \mbox{``Block''} & 
	\mbox{Addresses(A23:A00)} & \mbox{Data Mask} 
	& \mbox{ R/W} \\ \hline \hline
\mbox{LSB EM Tow} & 0\mbox{--}1 & 1 & 2 & 0\mbox{x}200000 
	& 0\mbox{x001F001F} & \mbox{WO} \\ \hline
\mbox{MSB EM Tow} & 0\mbox{--}1 & 1 & 2 & 0\mbox{x}200004 
	& 0\mbox{x001F001F} & \mbox{WO} \\ \hline
\mbox{LSB EM Tow} & 2\mbox{--}3 & 1 & 2 & 0\mbox{x}200008 
	& 0\mbox{x001F001F} & \mbox{WO} \\ \hline
\mbox{MSB EM Tow} & 2\mbox{--}3 & 1 & 2 & 0\mbox{x}20000\mbox{C} 
	& 0\mbox{x001F001F} & \mbox{WO} \\ \hline
\mbox{LSB EM Tow} & 4\mbox{--}5 & 1 & 2 & 0\mbox{x}200010 
	& 0\mbox{x001F001F} & \mbox{WO} \\ \hline
\mbox{MSB EM Tow} & 4\mbox{--}5 & 1 & 2 & 0\mbox{x}200014 
	& 0\mbox{x001F001F} & \mbox{WO} \\ \hline \hline
\mbox{LSB HAD Tow} & 0\mbox{--}1 & 1 & 2 & 0\mbox{x}200020 
	& 0\mbox{x001F001F} & \mbox{WO} \\ \hline
\mbox{MSB HAD Tow} & 0\mbox{--}1 & 1 & 2 & 0\mbox{x}200024 
	& 0\mbox{x001F001F} & \mbox{WO} \\ \hline
\mbox{LSB HAD Tow} & 2\mbox{--}3 & 1 & 2 & 0\mbox{x}200028 
	& 0\mbox{x001F001F} & \mbox{WO} \\ \hline
\mbox{MSB HAD Tow} & 2\mbox{--}3 & 1 & 2 & 0\mbox{x}20002\mbox{C} 
	& 0\mbox{x001F001F} & \mbox{WO} \\ \hline
\mbox{LSB HAD Tow} & 4\mbox{--}5 & 1 & 2 & 0\mbox{x}200030 
	& 0\mbox{x001F001F} & \mbox{WO} \\ \hline
\mbox{MSB HAD Tow} & 4\mbox{--}5 & 1 & 2 & 0\mbox{x}200034 
	& 0\mbox{x001F001F} & \mbox{WO} \\ \hline \hline
\mbox{LSB L2 EM Tow} & 0\mbox{--}1 & 1 & 2 & 0\mbox{x}200000 
	& 0\mbox{x001F001F} & \mbox{RO} \\ \hline
\mbox{MSB L2 EM Tow} & 0\mbox{--}1 & 1 & 2 & 0\mbox{x}200004 
	& 0\mbox{x001F001F} & \mbox{RO} \\ \hline
\mbox{LSB L2 EM Tow} & 2\mbox{--}3 & 1 & 2 & 0\mbox{x}200008 
	& 0\mbox{x001F001F} & \mbox{RO} \\ \hline
\mbox{MSB L2 EM Tow} & 2\mbox{--}3 & 1 & 2 & 0\mbox{x}20000\mbox{C} 
	& 0\mbox{x001F001F} & \mbox{RO} \\ \hline
\mbox{LSB L2 EM Tow} & 4\mbox{--}5 & 1 & 2 & 0\mbox{x}200010 
	& 0\mbox{x001F001F} & \mbox{RO} \\ \hline
\mbox{MSB L2 EM Tow} & 4\mbox{--}5 & 1 & 2 & 0\mbox{x}200014 
	& 0\mbox{x001F001F} & \mbox{RO} \\ \hline \hline
\mbox{LSB L2 HAD Tow} & 0\mbox{--}1 & 1 & 2 & 0\mbox{x}200020 
	& 0\mbox{x001F001F} & \mbox{RO} \\ \hline
\mbox{MSB L2 HAD Tow} & 0\mbox{--}1 & 1 & 2 & 0\mbox{x}200024 
	& 0\mbox{x001F001F} & \mbox{RO} \\ \hline
\mbox{LSB L2 HAD Tow} & 2\mbox{--}3 & 1 & 2 & 0\mbox{x}200028 
	& 0\mbox{x001F001F} & \mbox{RO} \\ \hline
\mbox{MSB L2 HAD Tow} & 2\mbox{--}3 & 1 & 2 & 0\mbox{x}20002\mbox{C} 
	& 0\mbox{x001F001F} & \mbox{RO} \\ \hline
\mbox{LSB L2 HAD Tow} & 4\mbox{--}5 & 1 & 2 & 0\mbox{x}200030 
	& 0\mbox{x001F001F} & \mbox{RO} \\ \hline
\mbox{MSB L2 HAD Tow} & 4\mbox{--}5 & 1 & 2 & 0\mbox{x}200034 
	& 0\mbox{x001F001F} & \mbox{RO} \\ \hline \hline
\mbox{LSB L1 EM Tow} & 0\mbox{--}1 & 1 & 2 & 0\mbox{x}200060 
	& 0\mbox{x001F001F} & \mbox{RO} \\ \hline
\mbox{MSB L1 EM Tow} & 0\mbox{--}1 & 1 & 2 & 0\mbox{x}200064 
	& 0\mbox{x000F000F} & \mbox{RO} \\ \hline
\mbox{LSB L1 EM Tow} & 2\mbox{--}3 & 1 & 2 & 0\mbox{x}200068 
	& 0\mbox{x001F001F} & \mbox{RO} \\ \hline
\mbox{MSB L1 EM Tow} & 2\mbox{--}3 & 1 & 2 & 0\mbox{x}20006\mbox{C} 
	& 0\mbox{x000F000F} & \mbox{RO} \\ \hline
\mbox{LSB L1 EM Tow} & 4\mbox{--}5 & 1 & 2 & 0\mbox{x}200070 
	& 0\mbox{x001F001F} & \mbox{RO} \\ \hline
\mbox{MSB L1 EM Tow} & 4\mbox{--}5 & 1 & 2 & 0\mbox{x}200074 
	& 0\mbox{x000F000F} & \mbox{RO} \\ \hline \hline
\mbox{LSB L1 Tot Ene} & 0\mbox{--}1 & 1 & 2 & 0\mbox{x}200040 
	& 0\mbox{x001F001F} & \mbox{RO} \\ \hline
\mbox{MSB L1 Tot Ene} & 0\mbox{--}1 & 1 & 2 & 0\mbox{x}200044 
	& 0\mbox{x001F001F} & \mbox{RO} \\ \hline
\mbox{LSB L1 Tot Ene} & 2\mbox{--}3 & 1 & 2 & 0\mbox{x}200048 
	& 0\mbox{x001F001F} & \mbox{RO} \\ \hline
\mbox{MSB L1 Tot Ene} & 2\mbox{--}3 & 1 & 2 & 0\mbox{x}20004\mbox{C} 
	& 0\mbox{x001F001F} & \mbox{RO} \\ \hline
\mbox{LSB L1 Tot Ene} & 4\mbox{--}5 & 1 & 2 & 0\mbox{x}200050 
	& 0\mbox{x001F001F} & \mbox{RO} \\ \hline
\mbox{MSB L1 Tot Ene} & 4\mbox{--}5 & 1 & 2 & 0\mbox{x}200054 
	& 0\mbox{x001F001F} & \mbox{RO} \\ \hline
\end{array}
$$
\end{table}

\clearpage

\begin{table}
\centering
\caption{Other Data Path Access Map}
\label{other data path}
$$
\begin{array}{||c||c|c|c|c|c|c||} \hline
\mbox{Memory} & \mbox{Towers} & \mbox{Size} & \mbox{``Block''} & 
	\mbox{Addresses(A23:A00)} & \mbox{Data Mask} 
	& \mbox{ R/W} \\ \hline \hline
\mbox{VME\_Loop} & \mbox{--} & 256 \times 8 & 3 
      	& 0\mbox{x}3003\mbox{FC}:0\mbox{x}30000 
	& 0\mbox{x000000FF} & \mbox{RO} \\ \hline
\mbox{TR\_DIAG} & \mbox{--} & 1 \times 8 & 7 & 0\mbox{x}700000 
	& 0\mbox{x000000FF} & \mbox{WO} \\ \hline
\mbox{TRIN\_FIFO} & \mbox{--} & 1 \times 8 & 7 & 0\mbox{x}700000 
	& 0\mbox{x000000FF} & \mbox{RO} \\ \hline
\mbox{L1\_FIFO} & 0\mbox{--}1 & 256 \times 32 & 2 
	& 0\mbox{x}2013\mbox{FC}:0\mbox{x}201000 
	& 0\mbox{xFFFFFFFF} & \mbox{WO} \\ \hline
\mbox{L1\_FIFO} & 2\mbox{--}3 & 256 \times 32 & 2 
	& 0\mbox{x}2023\mbox{FC}:0\mbox{x}202000 
	& 0\mbox{xFFFFFFFF} & \mbox{WO} \\ \hline
\mbox{L1\_FIFO} & 4\mbox{--}5 & 256 \times 32 & 2 
	& 0\mbox{x}2033\mbox{FC}:0\mbox{x}203000 
	& 0\mbox{xFFFFFFFF} & \mbox{WO} \\ \hline
\mbox{Static AL\_FIFO} & 0\mbox{--}1 & 1 \times 32 & 2 
	& 0\mbox{x}204000 
	& 0\mbox{xFFFFFFFF} & \mbox{RO} \\ \hline
\mbox{Static AL\_FIFO} & 2\mbox{--}3 & 1 \times 32 & 2 
	& 0\mbox{x}205000 
	& 0\mbox{xFFFFFFFF} & \mbox{RO} \\ \hline
\mbox{Static AL\_FIFO} & 4\mbox{--}5 & 1 \times 32 & 2 
	& 0\mbox{x}206000 
	& 0\mbox{xFFFFFFFF} & \mbox{RO} \\ \hline
\mbox{Strobe AL\_FIFO} & 0\mbox{--}1 & 256 \times 32 & 2 
	& 0\mbox{x}2073\mbox{FC}:0\mbox{x}207000 
	& 0\mbox{xFFFFFFFF} & \mbox{RO} \\ \hline
\mbox{Strobe AL\_FIFO} & 2\mbox{--}3 & 256 \times 32 & 2 
	& 0\mbox{x}2083\mbox{FC}:0\mbox{x}208000 
	& 0\mbox{xFFFFFFFF} & \mbox{RO} \\ \hline
\mbox{Strobe AL\_FIFO} & 4\mbox{--}5 & 256 \times 32 & 2 
	& 0\mbox{x}2093\mbox{FC}:0\mbox{x}209000 
	& 0\mbox{xFFFFFFFF} & \mbox{RO} \\ \hline
\mbox{Csum} & \mbox{--} & 1 \times 32 & 2 & 0\mbox{x}700004 
	& 0\mbox{xFFFFFFFF} & \mbox{RO} \\ \hline
\mbox{Csum MUX Int Reg} & \mbox{--} & 1 \times 17 & 2 
	& 0\mbox{x}700008 
	& 0\mbox{x0001FFFF} & \mbox{WO} \\ \hline
\mbox{Csum MUX Ouputs} & \mbox{--} & 1 \times 16 & 2 
	& 0\mbox{x}70000\mbox{C} 
	& 0\mbox{x0000FFFF} & \mbox{RO} \\ \hline
\mbox{EtSum} & \mbox{--} & 1 \times 8 & 2 & 0\mbox{x}700010 
	& 0\mbox{x000000FF} & \mbox{RW} \\ \hline
\end{array}
$$
\end{table}

\clearpage

The Tower Latch memory is not straight--forward.  This section
controls data access to the Tower Latch chips in {\bf TOWLAT}.  A user
is allowed to write data into the latches via the write--only(WO)
registers {\bf EM} and {\bf HAD Tow}.  By writing data to these
registers, one can provide artificial data to the rest of the L1
trigger as well as the L2 data path.  The LSB and MSB refer to the
least and most significant 5 bits.  The tower energies are all 10 bit
numbers, so to write a value to the EM tower, one must write the lower
and upper 5 bits separately.  This idea is the same for all aspects of
the Tower Latch chips.  Each set of 5 bits has its own clock, so it is
possible to download unique data to all towers.  The register titles
{\bf L2 EM} and {\bf HAD Tow} are read--only(RO) and allow access to
the data going to L2 from the Tower Latches.  The {\bf L1 EM Tow}
registers allow reading the Dirac EM energies.  Finally, the {\bf L1
Tot Ene} section contains the total energy for a tower, what has been
referred to as the jet energies.  The {\bf LSBHAD} data is also packed
into both the {\bf L1 EM Tow} and the {\bf L1 Tot Ene}.  The packing
of this data is discussed in reference \cite{Dirac Detailed}.

The rest of the memory is much easier to understand, so you can
relax now, right after you re--read the previous paragraph a few
times.  {\bf TR\_Diag} writes to the diagnostic register in the {\bf
Track} section.  This register lets the user provide fake input to
the tracking section, bypassing the tracking front panel connector.
{\bf TRIN\_FIFO} reads out the tracking FIFO.  {\bf VME\_Loop}
allows you to check a pair of buffers used within {\bf Track}.  {\bf
L1\_FIFO} provides the ability to write data into the L1 FIFO's.
Only 2 FIFO's can be written to at any given time, since the FIFO
clock is a global clock.  This is sufficient to test these chips.

There are 2 methods to read the alignment FIFO's in the {\bf
AL\_FIFO} section.  One strobes the data out of the FIFO and the
other merely spys on the outputs of the FIFO.  The corresponding
registers in table \ref{other data path} are obvious.  There are no
data buffers directly connected to the FIFOs in {\bf AL\_FIFO}.  In
order to read data from these FIFOs, Dirac uses the data buffers in
the {\bf Decision} block.  This means the Decision({\bf MLU\_T\_T})
SRAMs must be downloaded with a decodable pattern to determine the
state of the {\bf AL\_FIFO} outputs.  The most common pattern to use
should be an echo of the lower 8 address bits (In the memory count
from 0-255 then repeat to fill the memory up).

The {\bf Csum} register is dual--purpose.  When reading from this
register, you read from the trigger summing chips, thus getting the
output of the board.  When writing, you write into a set of input
latches in the Csum Multiplexer chip.  This allows the user to fake
data going off Dirac and to test the Csum Multiplexer chip.  The two
{\bf Csum MUX} registers allow manipulation of the Csum Multiplexer
chip.  The {\bf Csum MUX Int Reg} determines how the chip
multiplexes the 16 2--bit trigger summaries to the 10 1--bit and 3
2--bit summaries that actually are sent to CrateSum.  The actual
decoding of this register was previously described in the trigger
summary section.  Of course, one is allowed to spy on the outputs of
the multiplexer through {\bf Csum MUX Outputs}.  Finally, the {\bf
EtSum} register allows reading the output of the final energy
summing chip.  Additionally, one can write data to the backplane
latch that drives data to CrateSum.

\subsection{Control and Strobe Registers}

This memory is used to control the overall operation of DIRAC.  A
listing of all control registers is contained in table \ref{control
words}.  The descriptions of the various bits of the control and
strobe words are contained in tables \ref{control 0}, \ref{control 1},
\ref{strobes} and \ref{delays}.  The {\bf Module ID} memory is for an
ID prom that will contain a ``special'' ASCII code to identify this
board as a DIRAC board.  The {\bf Bunch Offset} contains a 3 bit value
designating the postition of Dirac in the L1 pipeline.  This value is
only 3 bits because the bunch counter chips in the {\bf Control}
section must be programmed within 8 CDF clocks of the real position.
The {\bf Full} and {\bf Empty Flag} registers access data in the Error
chip on Dirac.  This chip monitors the empty or full state of all
Dirac FIFOs.  If a chip becomes full, an error signal is sent to the
master control chip (Brain) and an appropriate action is taken.  These
registers are read--writable, allowing the user to mask off any FIFO's
Full or Empty status.  This masking ability is neccessary to allow
Dirac to function with a ``Bad'' channel.  The Empty flags are fed to
the global timing chip(Heart) to handle the special latency timing of
the Dirac FIFOs.  There are 6 L1 FIFOs storing trigger decisions and 1
L1 FIFO for the bunch counter; the extra bit is a spare.  There are
also 6 alignment FIFOs storing energy data and 1 storing {\bf LSBHAD}
data.  The {\bf Track} FIFO flags are the 8th bit of the {\bf AL}
flags.  The packing of the data during reading of the flags is
discussed in note 9999.\cite{Dirac Detailed} The {\bf EM} and {\bf HAD
Masks} registers allow the user to mask off any Dirac tower energies.
The value output from the {\bf TOWLAT} section for the masked tower is
zero and does not contribute to the total energy output of Dirac.


	Regarding Control\_0 note that to write to the MLU memories, one must be in LOAD mode and Bit 6 and 7 of Control\_0 must be off (0). Also to RESET Dirac via VME, that is using the bit0 of Control0 strobe, the board must also be in LOAD mode. (Of course in normal operation the board receives the CDF reset signal while in RUN mode, and acts appropriately, by clearing error flags and fifos).


\begin{table}
\centering
\caption{Control and Strobe Words}
\label{control words}
$$
\begin{array}{||c||c|c|c|c|c|c|c||} \hline
\mbox{Memory} & \mbox{Size} & \mbox{``Block''} & 
	\mbox{Addresses(A23:A00)} & \mbox{Data Mask} 
	& \mbox{Offset} & \mbox{ R/W} \\ \hline \hline
\mbox{Control\_0} & 1 \times 10 & 0 & 0\mbox{x}000000 
	&0\mbox{xFFC00000} &  22 & \mbox{RW} \\ \hline
\mbox{Control\_1} & 1 \times 10 & 0 & 0\mbox{x}000004 
	& 0\mbox{xFFC00000} & 22 & \mbox{RW} \\ \hline
\mbox{Strobes} & 1 \times 9 & 0 & 0\mbox{x}000008 
	& 0\mbox{x7FC00000} & 23 & \mbox{WO} \\ \hline
\mbox{Delays} & 1 \times 10 & 0 & 0\mbox{x}00000\mbox{C} 
	& 0\mbox{xFFC00000} & 22 & \mbox{RW} \\ \hline
\mbox{Module ID} & 32 \times 8 & 1 & 0\mbox{x}10007\mbox{C}:0\mbox{x}100000 
	& 0\mbox{xFF000000} & 24 & \mbox{RO} \\ \hline
\mbox{Bunch Offset} & 1 \times 3 & 7 & 0\mbox{x}700020 
	& 0\mbox{x00000007} & 0  & \mbox{WO} \\ \hline
\mbox{L1 Full Flags} & 1 \times 8 & 7 & 0\mbox{x}700030 
	& 0\mbox{x000000FF} & 0  & \mbox{RW} \\ \hline
\mbox{AL Full Flags} & 1 \times 8 & 7 & 0\mbox{x}700034 
	& 0\mbox{x000000FF} & 0  & \mbox{RW} \\ \hline
\mbox{L1 Empty Flags} & 1 \times 8 & 7 & 0\mbox{x}700038 
	& 0\mbox{x000000FF} & 0  & \mbox{RW} \\ \hline
\mbox{AL Empty Flags} & 1 \times 8 & 7 & 0\mbox{x}70003\mbox{C} 
	& 0\mbox{x000000FF} & 0  & \mbox{RW} \\ \hline
\mbox{EM Masks} & 1 \times 6 & 7 & 0\mbox{x}000010 
	& 0\mbox{x0FC00000} & 22 & \mbox{RW} \\ \hline
\mbox{HAD Masks} & 1 \times 6 & 7 & 0\mbox{x}000014 
	& 0\mbox{x0FC00000} & 22 & \mbox{RW} \\ \hline
\end{array}
$$
\end{table}
\clearpage

\begin{table}
\centering
\caption{Control\_0 Register}
\label{control 0}
$$
\begin{array}{||c|c|c||c|c||} \cline{1-2}
\multicolumn{2}{||c|}{\mbox{Bit}} & \multicolumn{3}{c}{} \\ \hline
\mbox{Rel} & \mbox{Abs} & \mbox{Bit Name} & \mbox{Description} & \mbox{RW} \\ \hline \hline
0 & 22 & \mbox{RESET} & \mbox{Board level reset} & \mbox{WO} \\ \hline
1 & 23 & \mbox{LOAD} & \mbox{ON -- {\bf LOAD} mode---Diagnostic mode} 
	& \mbox{RW} \\
  & & & \mbox{OFF -- {\bf RUN} mode---Data Taking mode} & \\ \hline
2 & 24 & \mbox{CLK\_MODE} & \mbox{ON --- use CDF clock from P2} 
	& \mbox{RW} \\
  & &  & \mbox{OFF --- use VME SYSCLK(halved)}& \\ \hline
3 & 25 & \mbox{FTOW\_EN} & \mbox{Enable front panel L2 drivers} 
	& \mbox{RW} \\ \hline 
4 & 26 & \mbox{TRACK\_SRC} & \mbox{ON --- use front panel connector} & \mbox{RW} \\
 & &  & \mbox{as the source of tracking information} & \\
 & &  & \mbox{OFF --- use tracking diagnostics register} & \\
 & &  & \mbox{to fake the front panel input} & \\ \hline
5 & 27 & \mbox{SPARE} & \mbox{Spare DIRAC Bit} 
	& \mbox{RW} \\ \hline
6 & 28 & \mbox{MLU\_FIFO\_EN} & \mbox{Enable all MLUs and FIFOs} 
	& \mbox{RW} \\
 & &  & \mbox{while in {\bf LOAD} mode} & \\ \hline
7 & 29 & \mbox{MLU\_READ\_MODE} & \mbox{Place all MLUs in Read Mode} 
	& \mbox{RW} \\
 & &  & \mbox{while in {\bf LOAD} mode} & \\ \hline
8 & 30 & \mbox{AUX\_SUM\_EN0} & \mbox{Enable AUX Endwall Sum 5+12=5} 
	& \mbox{RW} \\ \hline
9 & 31 & \mbox{AUX\_SUM\_EN1} & \mbox{Enable AUX Endwall Sum 7+12=7} 
	& \mbox{RW} \\ \hline
\end{array}
$$
\end{table}
\clearpage

\begin{table}
\centering
\caption{Control\_1 Register}
\label{control 1}
$$
\begin{array}{||c|c|c||c|c||} \cline{1-2}
\multicolumn{2}{||c|}{\mbox{Bit}} & \multicolumn{3}{c}{} \\ \hline
\mbox{Rel} & \mbox{Abs} & \mbox{Bit Name} & \mbox{Description} & \mbox{R/W} \\ \hline \hline
0 & 22 & \mbox{L1\_ACC} & \mbox{Data is written from L1 FIFO to L2 DAQ} 
	& \mbox{WO} \\
 & & & \mbox{buffer specified by {\bf L1\_ADDR}(see below) This is} & \\
 & & & \mbox{used to fake a {\bf L1A} during diagnostics} & \\ \hline
2\mbox{:}1 &24\mbox{:}23 & \mbox{L1\_ADDR} & \mbox{Address to store event} 
	& \mbox{RW} \\ 
 & & & \mbox{for a fake L1 Accept} & \\ \hline
4\mbox{:}3 &26\mbox{:}25 & \mbox{ET\_THRESH} & \mbox{Energy threshold for EtSum} 
	& \mbox{RW} \\ 
 & & & \mbox{If a towers energy is below this value in bits,} & \\
 & & & \mbox{then the tower does not contribute to the sum.} & \\
 & & & \mbox{(See Table~\ref{Sum Threshold} for details)} & \\ \hline
% E.g.  11 corresponds to the 3 LSBs or a count of 8} & \\
% & & & \mbox{Each LSB is 0.250 GeV or 0.500 GeV, depending on bit8 below} & \\ \hline

5 & 27 & \mbox{ETSUM\_EN} & \mbox{Enable Backplane drivers for {\bf EtSum}} 
	& \mbox{RW} \\ \hline
6 & 28 & \mbox{CSUM\_EN} & \mbox{Enable Backplane drivers for {\bf CardSum}} 
	& \mbox{RW} \\ \hline
7 & 29 & \mbox{HAD\_EM\_SEL} & \mbox{Select which bits determine} 
	& \mbox{RW} \\
 & & &\mbox{the {\bf LSBHAD} Energy.} & \\
 & & &\mbox{ON --- bits (3:1) of HAD Energy (0.250 GeV lsb)} & \\ 
 & & &\mbox{OFF --- bits (2:0) of HAD Energy (0.125 GeV lsb)} & \\ \hline
8 & 30 &\mbox{TOW\_GRAN} & \mbox{Set the Tower Energy Granularity} 
	& \mbox{RW} \\
 & & & \mbox{for L1 Decisions.} & \\
 & & & \mbox{ON --- 0.500 GeV Least Count } & \\
 & & & \mbox{OFF --- 0.250 GeV Least Count } & \\ \hline
9 & 31 &\mbox{AUX\_ENABLE} & \mbox{Enable Tower Data coming from AUX} 
	& \mbox{RW} \\ \hline
\end{array}
$$
\end{table}

\clearpage

The {\bf Strobes} word (table \ref{strobes}) is used to issue a clock
signal to a specific section of Dirac.  This is accomplished by
writing to the ``Brain'' chip which passes the data to the ``Heart''
chip.  The ``Heart'' chip then issues the appropriate clock(s).
Usually a single clock is issued, but it is possible to clock multiple
sections of Dirac.  The {\bf Delays} word (table~\ref{delays})
specifies the delay from the interaction for data to arrive at Dirac.
Two times are needed, one for calorimetry energies and another for
tracking information (t$_{\mbox{Calorimetry}}$ and
t$_{\mbox{Tracking}}$, respectively).  The exact delays can be
determined from the following formulae,
\begin{eqnarray*}
\mbox{t}_{\mbox{Calorimetry}} \left( \mbox{ns} \right) & = & \left( 
	\mbox{\bf CALOR\_DEL} + 12 \right) * 132 + \left( 
	\mbox{\bf CALOR\_TAP}  \right) * 25 + \tau_{\mbox{PLD}} \\
\mbox{t}_{\mbox{Tracking}} \left( \mbox{ns} \right) & = & \left( 
	\mbox{\bf TRACK\_DEL} + 15 \right) * 132 + \left( 
	\mbox{\bf TRACK\_TAP}  \right) * 25 + \tau_{\mbox{PLD}} \\
\end{eqnarray*}
where $\tau_{\mbox{PLD}}$ is the delay imposed by the timing control
logic and is approximately 32 ns for a EPM7128LC84--10(the chip used
for the ``Heart'').  The range of t$_{\mbox{Tracking}}$ is 2012 to
3011 ns and t$_{\mbox{Calorimetry}}$ is 1616 to 2615 ns.
	

	With these assignments Dirac obeys the specifications of the current L1 timing diagram. Note that Tracking Data must arrive at Dirac at least 3 clocks AFTER Tower Data. Therefore when adjusting the previous delays, it's understood that this condition is always met. Failure to do so will cause Tower and Tracking data misalignments in Dirac. A final practical note on adjusting B0 Offset: Currently this should be set equal to the the number of TRACK\_DEL, so that the first event processed by Dirac, presumably B0 after the previous timing adjustments, will have the 00 marker for the B0 counter.


\begin{table}
\centering
\caption{Strobes Register}
\label{strobes}
$$
\begin{array}{||c|c|c||c|c||} \cline{1-2}
\multicolumn{2}{|c|}{\mbox{Bit}} & \multicolumn{3}{c}{} \\ \hline
\mbox{Rel} & \mbox{abs} & \mbox{Bit Name} & \mbox{Description} & \mbox{R/W} \\ \hline \hline
0 & 23 &\mbox{TOWER\_IN} & \mbox{Latch the data into the Tower} & \mbox{WO} \\
  & & & \mbox{Latch chip from the AUX card} & \\ \hline
1 & 24 &\mbox{ALFIFO\_IN} & \mbox{Strobe data into {\bf AL\_FIFO}} 
	& \mbox{WO} \\
  & & & \mbox{and input latches of {\bf EtSum}} & \\ \hline
2 & 25 &\mbox{ETSUM\_IN} & \mbox{Strobe data into of {\bf EtSum} section} 
	& \mbox{WO} \\ \hline
3 & 26 &\mbox{ETSUM\_OUT} & \mbox{Strobe data out of {\bf EtSum}} 
	& \mbox{WO} \\
  & & & \mbox{and across P3 to CS} & \\ \hline
4 & 27 & \mbox{ALFIFO\_OUT} & \mbox{Strobe data out of {\bf AL\_FIFO}} 
	& \mbox{WO} \\ \hline
5 & 28 &\mbox{TRACK\_IN} & \mbox{Clock the data into the tracking} & \mbox{WO} \\
  & & & \mbox{FIFO from either the front panel or the} & \\
  & & & \mbox{diagnostic register.  Source is determined by} & \\
  & & & \mbox{the state of the {\bf TRACK\_SRC} bit of {\bf Control\_0}} & \\ \hline
6 & 29 & \mbox{L1FIFO\_IN} & \mbox{Strobe data into {\bf DAQ} L1 FIFO} 
	& \mbox{WO} \\ \hline
7 & 30 & \mbox{CSUM\_IN} & \mbox{Strobe data into {\bf CardSum}} 
	& \mbox{WO} \\ \hline
8 & 31 &\mbox{L1FIFO\_OUT} & \mbox{Strobe data out of the {\bf DAQ} L1 FIFO} 
	& \mbox{WO} \\ \hline
\end{array}
$$
\end{table}
\clearpage

\begin{table}
\centering
\caption{Delays Register}
\label{delays}
$$
\begin{array}{||c|c|c||c|c||} \cline{1-2}
\multicolumn{2}{|c|}{\mbox{Bit}} & \multicolumn{3}{c}{} \\ \hline
\mbox{Rel}& \mbox{Abs} & \mbox{Bit Name} & \mbox{Description} 
	& \mbox{R/W} \\ \hline \hline
2\mbox{:}0 & 24\mbox{:}22 & \mbox{CALOR\_DEL} & \mbox{Interaction to t}_{\mbox{Calorimetry}}
	\mbox{ delay --- coarse} & \mbox{R/W} \\ \hline
4\mbox{:}3 & 26\mbox{:}25 & \mbox{CALOR\_TAP} & \mbox{Interaction to t}_{\mbox{Calorimetry}}
	\mbox{ delay --- fine} & \mbox{R/W} \\ \hline
7\mbox{:}5 & 29\mbox{:}27 & \mbox{TRACK\_DEL} & \mbox{Interaction to t}_{\mbox{Track}}
	\mbox{ delay --- coarse} & \mbox{R/W} \\ \hline
9\mbox{:}8 & 31\mbox{:}30 & \mbox{TRACK\_TAP} & \mbox{Interaction to t}_{\mbox{Track}}
	\mbox{ delay --- fine} & \mbox{R/W} \\ \hline
\end{array}
$$
\end{table}

\clearpage

\eject
{\center \Large \bf APPENDIX}
\appendix
\section{DIRAC VME Interface}

DIRAC provides the circuitry for A32 addressing, D32 and D32(BLT) data
transfers through the VME bus protocol.  DIRAC allows address
pipelining and responds to both supervisory and non-privileged
accesses.  The address modifier bits and the transfer types supported
by DIRAC are summarized in table \ref{am table}.
Since all transfers are quad byte and unaligned data transfers are not
supported, LWORD* is low, address bit A01 is ignored and data strobes
DS0* and DS1* are ORed together.  A module is selected in the VME
crate by using a 5--bit geographical address GA(4:0) hardwired on the
P1 backplane.  The address defines a 128 Mbyte zone from the full 4
Gbyte VME address space (please refer to figure \ref{address space}).
This zone is addressed if A31:A27 equals GA4:GA0.  DIRAC uses only 16
Mbyte(A26:A24 = 0) of the 128 Mbyte zone.

\begin{table}
\centering
\caption{Address Modifiers}
\label{am table}
$$
\begin{array}{||c|c||c||} \hline
\mbox{AM(Hex)} & \mbox{Address Bits} & \mbox{Transfer Type}\\ \hline \hline
09 & 32 & \mbox{Extended non--privileged data access}\\ \hline
0\mbox{B} & 32 & \mbox{Extended non--privileged block transfer} \\ \hline
0\mbox{D} & 32 & \mbox{Extended supervisory data access} \\ \hline
0\mbox{F} & 32 & \mbox{Extended supervisory block transfer} \\ \hline
\end{array}
$$
\end{table}
\clearpage

\section{Run Startup: Cold Start}

Before {\bf EVERY} Cold Start, the following registers must be
configured with valid data. For this the board needs to be set into LOAD mode (bit 1 of Control0 ON) and bits 6 and 7 of Control1 OFF, and a VME RESET issued (bit 0 of Control0). (This last one is just to make sure that previous error conditions are erased).

\begin{itemize}
\item MLU\_T\_T (All 3 sets of SRAMs) --- The Trigger Tables. Each SRAM has 32Kx(32 bits), for a total of 3x32K words, each word a 4 byte one. So a total of 384 Kbytes/board.
\item TR\_FAN\_OUT --- The Tracking Fan--Out Information. 256x(24 bits). 
\item Csum MUX Int Reg --- The CSUM MUX Internal Register to
determine which trigger bits get passed to CrateSum. 17 bits.
\item Control\_0 --- Various DIRAC State Settings. 10 bits.
\item Control\_1 --- Various DIRAC State Settings. 10 bits.
\item Delays --- The Timing Delays for Pipeline Stages. 10 bits.
\item Bunch Offset --- The Number of Bunches DIRAC is in the Pipeline. 7 bits.
\item EM Masks --- Masking Register for EM Energies. 6 bits
\item HAD Masks --- Masking Register for HAD Energies. 6 bits
\end{itemize}
If any of the above registers are neglected at run startup, any data
taken can be considered invalid.

A total of about 400 Kbytes/board needs to be downloaded. If within a crate there is no $\Phi$ dependence and 
the only $\eta$ dependence is the difference between PLUG and CENTRAL, then a total of about 800 Kbytes/crate needs to be downloaded.
  
\bigskip
\medskip
The following registers are for masking bad channels inside Dirac. In a normally GOOD working Dirac, they 
assume default values such that no L1 or AL Fifos are masked. So for a normally working GOOD board, they need NOT to be downloaded.


\begin{itemize}
\item L1 Full Flags --- Masking Register for FIFO Full Flags.
\item AL Full Flags --- Masking Register for FIFO Full Flags.
\item L1 Empty Flags --- Masking Register for FIFO Empty Flags.
\item AL Empty Flags --- Masking Register for FIFO Empty Flags.
\end{itemize}

\section{Known ``features''}

The following ``features'' were added after ``careful'' consideration:
\begin{itemize}
\item Module ID. 

When Addresses 0x10007C:0x100000 are read, the upper 8 bits of data of each of these addresses have the ASCII equivalents of: 00XX 005 DIRAC. Beautiful, ahn~? The only thing is that instead of reading the board serial number, you get XX. But when you read the DAQ buffers, the serial number indeed is there, in its right place. Getting the serial number right also in the module ID would have required to route more input lines into one chip (Control) that did not have more input pins available. Either way, who needs the serial numbers on the board ID, anyway?

\item Serial Number switches.

When setting the switches that set the board serial number (switches S1), the following happens:
to set bit 6 (staring counting at 0) must set switch number 9 (starting counting at 1). To set bit 7, must set switch number 7; to set bit 8, switch number 8. This happened because on the schematics the switch counting goes as 1 2 3 4 5 6 9 7 8 10, instead of 1 2 3 4 5 6 7 8 9 10. The reasons for this are ``too long to explain here''...

\item Sum Saturation in Sum $E_T$\ Calculation (3/16/05)

The current version of the firmware for the ETINP chip (in use since
the begining of the run) does not correctly handle the case of a single tower
at full scale.  In each stage of the summing, if the input or the sum
is at full scale, the output is supposed to be set to full scale.
However, the first summing stage of the Sum $E_T$\ path which adds two
towers together does not handle the case of one of the single tower
inputs being at full scale.  This is the result of dropping the lsb
out of the sum and shifting the full scale up.  This bug is independent of 
selected tower granularity.  In principle this is simple to fix but it
may not be practical because of the age of the EPLDs used and the required 
software to modify the firmware.

\end{itemize}

\include{bibdirac_spec}

\end{document}









