SVT GhostBuster board
This page contains documents, technical data, etc., about the
CDF SVT GhostBuster board that deletes duplicate tracks
from the SVT output stream, corrects SVT tracks dynamically for
beam position offsets, provides diagnostic readout of SVT cable
data and timing, and in SVT's first trigger test runs in late 2001 even
served as an ad-hoc Level2 trigger processor. The basic architecture
of the GB is SVT input + big programmable chip + SVT output.
The ghostbuster board was proposed in collaboration with Mel Shochet,
built in collaboration with Mircea Bogdan, and programmed in collaboration
with Franco Spinella (for trigger test runs) and Takasumi Maruyama (for
beam subtraction and duplicate removal).
Bill's GhostBuster board project logbook
Schematics:
top,
in,
logic,
out,
l2out,
vme,
vmechip,
P0,
P1,
P2,
power
Layout
Extremely primitive firmware
An old set of Firmware desiderata;
and a newer (6/02) feature list
Misc notes for future GB maintenance
A few notes on compiling the code
An incomplete example of
fixed-point beam subtraction code
Here are the Python program that I used to
generate Mentor Graphics QuickSim test vectors for the MMB, GB, FADC,
HF boards, and the program that I was working on
to generate Altera Quartus test vectors for the GB. If you want to
use this, more development will be needed.
Latest development firmware directories
(in CVS) for
processor,
utility, and
vmechip programs
Last updated on $Date: 2003/06/27 17:00:55 $ (UTC)
