| function | hex address (bytes) | access | comments | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| start(+) | range | |||||||||||
| FSM check read | 0xY00014 | 4 | R | FSM read. | ||||||||
| Flash Memory block pointing | 0xY0000c | 4 | R/W | Point preferable block to read/write. Up to 6 bits | ||||||||
| Flash Memory Read/Write | 0x3eXXXX | 4 | R/W | XXXX points the stored addresses. e.g. address 1 : 0x1<<2 == 0x4 | ||||||||
| e.g. address 2 : 0x2<<2 == 0x8 | ||||||||||||
| Spy count read/clear | 0xY00018 | 4 | R/W | SPY counter pointer. If we set write, we clear and initilize SPY counter. | ||||||||
| Spy Buffer read | 0xY4XXXX | 4 | R | SPY buffer read. XXXX points address of data, same as Flash Memory | ||||||||
| Spy Time count read/clear | 0xY0001c | 4 | R/W | SPY time pointer. If we write, we clear and initilize SPY time counter. | ||||||||
| Spy Time Buffer read | 0xY6XXXX | 4 | R | Timing SPY buffer read. XXXX points address of data, same as SPY | ||||||||
| FPGA FIFO read/write | 0x3cXXXX | 4 | R/W | Write data to FPGA FIFO directly, read data in FIFO | ||||||||
| FIFO status | 0x000020 | 4 | R | 0bit: hardware FIFO not empty, 1bit: hardware FIFO Full | ||||||||
| 2bit: hardwareFIFO almost full, 3bit: HOLD signiture | ||||||||||||
| 4bit: FPGA FIFO !empty, 5bit: L1A FIFO !empty | ||||||||||||
| Buf0 L1A got time read | 0xY00040 | 4 | R | Read L1A or SVT data coming timing in Buffer0 | ||||||||
| Buf1 L1A got time read | 0xY00044 | 4 | R | Read L1A or SVT data coming timing in Buffer1 | ||||||||
| Buf2 L1A got time read | 0xY00048 | 4 | R | Read L1A or SVT data coming timing in Buffer2 | ||||||||
| Buf3 L1A got time read | 0xY0004c | 4 | R | Read L1A or SVT data coming timing in Buffer3 | ||||||||
| (*) TM=only possible in Test Mode, FZ=only possible if FREEZE is asserted, FZ/TM=both(o) | ||||||||||||
| (o) Reading Spy Buffers in TM requires FZ or Freeze VME (FZV) being set | ||||||||||||
| (+) YY=[GA4,GA3,GA2,GA1,GA0,0,0,0], X=dont' care | ||||||||||||