-- -- Copyright (C) 1988-2001 Altera Corporation -- Any megafunction design, and related net list (encrypted or decrypted), -- support information, device programming or simulation file, and any other -- associated documentation or information provided by Altera or a partner -- under Altera's Megafunction Partnership Program may be used only to -- program PLD devices (but not masked PLD devices) from Altera. Any other -- use of such megafunction design, net list, support information, device -- programming or simulation file, or any other related documentation or -- information is prohibited for any other purpose, including, but not -- limited to modification, reverse engineering, de-compiling, or use with -- any other silicon devices, unless such use is explicitly licensed under -- a separate agreement with Altera or a megafunction partner. Title to -- the intellectual property, including patents, copyrights, trademarks, -- trade secrets, or maskworks, embodied in any such megafunction design, -- net list, support information, device programming or simulation file, or -- any other related documentation or information provided by Altera or a -- megafunction partner, remains with Altera, the megafunction partner, or -- their respective licensors. No other licenses, including any licenses -- needed under any third party's intellectual property, are provided herein. -- CHIP vme_interface BEGIN |_delayed_ds : INPUT_PIN = 142; |_as : INPUT_PIN = 139; |_BERR : BIDIR_PIN = 111; |_DTACK : BIDIR_PIN = 121; |_MODSEL : OUTPUT_PIN = 122; |_delayed_modsel : INPUT_PIN = 123; |_vme_data_str : OUTPUT_PIN = 130; |dir_trans : OUTPUT_PIN = 131; |Address31 : INPUT_PIN = 132; |Address30 : INPUT_PIN = 134; |Address29 : INPUT_PIN = 135; |Address28 : INPUT_PIN = 136; |Address27 : INPUT_PIN = 137; |Address26 : INPUT_PIN = 144; |Address25 : INPUT_PIN = 145; |Address24 : INPUT_PIN = 146; |_GA4 : INPUT_PIN = 147; |_GA3 : INPUT_PIN = 149; |_GA2 : INPUT_PIN = 150; |_GA1 : INPUT_PIN = 151; |_GA0 : INPUT_PIN = 152; |Address2 : INPUT_PIN = 153; |Address3 : INPUT_PIN = 158; |Address4 : INPUT_PIN = 159; |Address5 : INPUT_PIN = 160; |Address6 : INPUT_PIN = 10; |Address7 : INPUT_PIN = 11; |Address8 : INPUT_PIN = 12; |Address9 : INPUT_PIN = 13; |Address10 : INPUT_PIN = 14; |Address11 : INPUT_PIN = 15; |Address12 : INPUT_PIN = 16; |Address13 : INPUT_PIN = 18; |Address14 : INPUT_PIN = 19; |Address15 : INPUT_PIN = 20; |Address16 : INPUT_PIN = 21; |Address17 : INPUT_PIN = 23; |Address18 : INPUT_PIN = 24; |Address19 : INPUT_PIN = 25; |Address20 : INPUT_PIN = 27; |Address21 : INPUT_PIN = 28; |Address22 : INPUT_PIN = 29; |Address23 : INPUT_PIN = 30; |_iack : INPUT_PIN = 31; |AM4 : INPUT_PIN = 32; |AM3 : INPUT_PIN = 33; |AM2 : INPUT_PIN = 41; |AM1 : INPUT_PIN = 43; |AM0 : INPUT_PIN = 48; |_vme_write : INPUT_PIN = 49; |AM5 : INPUT_PIN = 50; |_DS0 : INPUT_PIN = 51; |_lword : INPUT_PIN = 52; |_DS1 : INPUT_PIN = 53; |fromtapdel9 : INPUT_PIN = 54; |fromtapdel8 : INPUT_PIN = 56; |fromtapdel7 : INPUT_PIN = 57; |fromtapdel6 : INPUT_PIN = 58; |fromtapdel5 : INPUT_PIN = 59; |fromtapdel4 : INPUT_PIN = 62; |fromtapdel3 : INPUT_PIN = 63; |fromtapdel2 : INPUT_PIN = 64; |fromtapdel1 : INPUT_PIN = 65; |fromtapdel0 : INPUT_PIN = 67; |totapdel : OUTPUT_PIN = 68; |vmespare : OUTPUT_PIN = 69; |vmeds : OUTPUT_PIN = 70; |vmeas : OUTPUT_PIN = 71; |vme_write : OUTPUT_PIN = 72; |vme_address2 : OUTPUT_PIN = 73; |vme_address3 : OUTPUT_PIN = 78; |vme_address4 : OUTPUT_PIN = 80; |vme_address5 : OUTPUT_PIN = 88; |vme_address6 : OUTPUT_PIN = 89; |vme_address7 : OUTPUT_PIN = 90; |vme_address8 : OUTPUT_PIN = 91; |vme_address9 : OUTPUT_PIN = 92; |vme_address10 : OUTPUT_PIN = 93; |vme_address11 : OUTPUT_PIN = 94; |vme_address12 : OUTPUT_PIN = 96; |vme_address13 : OUTPUT_PIN = 97; |vme_address14 : OUTPUT_PIN = 98; |vme_address15 : OUTPUT_PIN = 100; |vme_address16 : OUTPUT_PIN = 101; |vme_address17 : OUTPUT_PIN = 102; |vme_address18 : OUTPUT_PIN = 103; |vme_address19 : OUTPUT_PIN = 105; |vme_address20 : OUTPUT_PIN = 106; |vme_address21 : OUTPUT_PIN = 107; |vme_address22 : OUTPUT_PIN = 108; |vme_address23 : OUTPUT_PIN = 109; DEVICE = EPM7128SQC160-7; END; DEFAULT_DEVICES BEGIN AUTO_DEVICE = EPM7256SRC208-10; AUTO_DEVICE = EPM7192SQC160-10; AUTO_DEVICE = EPM7128SQC160-7; AUTO_DEVICE = EPM7128STC100-7; AUTO_DEVICE = EPM7128SQC100-7; AUTO_DEVICE = EPM7128SLC84-7; AUTO_DEVICE = EPM7064STC100-7; AUTO_DEVICE = EPM7064STC44-7; AUTO_DEVICE = EPM7064SLC44-7; ASK_BEFORE_ADDING_EXTRA_DEVICES = ON; END; TIMING_POINT BEGIN DEVICE_FOR_TIMING_SYNTHESIS = EPM7128SQC160-7; MAINTAIN_STABLE_SYNTHESIS = ON; CUT_ALL_CLEAR_PRESET = ON; CUT_ALL_BIDIR = ON; END; IGNORED_ASSIGNMENTS BEGIN FIT_IGNORE_TIMING = OFF; IGNORE_LC_ASSIGNMENTS = ON; IGNORE_CLIQUE_ASSIGNMENTS = OFF; IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF; IGNORE_TIMING_ASSIGNMENTS = OFF; IGNORE_CHIP_ASSIGNMENTS = OFF; IGNORE_DEVICE_ASSIGNMENTS = OFF; IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF; DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF; IGNORE_PIN_ASSIGNMENTS = OFF; END; GLOBAL_PROJECT_DEVICE_OPTIONS BEGIN MAX7000B_ENABLE_VREFB = OFF; MAX7000B_ENABLE_VREFA = OFF; MAX7000B_VCCIO_IOBANK2 = 3.3V; MAX7000B_VCCIO_IOBANK1 = 3.3V; CONFIG_EPROM_PULLUP_RESISTOR = ON; CONFIG_EPROM_USER_CODE = FFFFFFFF; FLEX_CONFIGURATION_EPROM = AUTO; MAX7000AE_ENABLE_JTAG = ON; MAX7000AE_USER_CODE = FFFFFFFF; RESERVED_LCELLS_PERCENT = 0; RESERVED_PINS_PERCENT = 0; SECURITY_BIT = OFF; USER_CLOCK = OFF; RELEASE_CLEARS = OFF; ENABLE_DCLK_OUTPUT = OFF; DISABLE_TIME_OUT = OFF; CONFIG_SCHEME = ACTIVE_SERIAL; FLEX8000_ENABLE_JTAG = OFF; DATA0 = RESERVED_TRI_STATED; DATA1_TO_DATA7 = UNRESERVED; nWS_nRS_nCS_CS = UNRESERVED; RDYnBUSY = UNRESERVED; RDCLK = UNRESERVED; SDOUT = RESERVED_DRIVES_OUT; ADD0_TO_ADD12 = UNRESERVED; ADD13 = UNRESERVED; ADD14 = UNRESERVED; ADD15 = UNRESERVED; ADD16 = UNRESERVED; ADD17 = UNRESERVED; CLKUSR = UNRESERVED; nCEO = UNRESERVED; ENABLE_CHIP_WIDE_RESET = OFF; ENABLE_INIT_DONE_OUTPUT = OFF; FLEX10K_JTAG_USER_CODE = 7F; CONFIG_SCHEME_10K = PASSIVE_SERIAL; MAX7000S_USER_CODE = FFFF; FLEX10K_ENABLE_LOCK_OUTPUT = OFF; MAX7000S_ENABLE_JTAG = ON; MULTIVOLT_IO = OFF; CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL; FLEX6000_ENABLE_JTAG = OFF; FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF; FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON; FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF; AUTO_RESTART = ON; ENABLE_CHIP_WIDE_OE = OFF; END; GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS BEGIN DEVICE_FAMILY = MAX7000S; MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF; AUTO_GLOBAL_CLOCK = ON; AUTO_GLOBAL_CLEAR = ON; AUTO_GLOBAL_PRESET = ON; AUTO_GLOBAL_OE = ON; AUTO_REGISTER_PACKING = OFF; ONE_HOT_STATE_MACHINE_ENCODING = OFF; AUTO_OPEN_DRAIN_PINS = ON; AUTO_IMPLEMENT_IN_EAB = OFF; STYLE = FAST; AUTO_FAST_IO = ON; OPTIMIZE_FOR_SPEED = 10; MULTI_LEVEL_SYNTHESIS_MAX9000 = OFF; END; COMPILER_PROCESSING_CONFIGURATION BEGIN SMART_RECOMPILE = OFF; RPT_FILE_LCELL_INTERCONNECT = OFF; DESIGN_DOCTOR = OFF; DESIGN_DOCTOR_RULES = EPLD; FUNCTIONAL_SNF_EXTRACTOR = OFF; TIMING_SNF_EXTRACTOR = ON; OPTIMIZE_TIMING_SNF = OFF; LINKED_SNF_EXTRACTOR = OFF; RPT_FILE_EQUATIONS = ON; RPT_FILE_HIERARCHY = ON; RPT_FILE_USER_ASSIGNMENTS = ON; GENERATE_AHDL_TDO_FILE = OFF; PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF; FITTER_SETTINGS = ADVANCED; END; COMPILER_INTERFACES_CONFIGURATION BEGIN VHDL_FLATTEN_BUS = OFF; VERILOG_FLATTEN_BUS = OFF; VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE; VHDL_READER_VERSION = VHDL93; XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC; XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON; XNF_GENERATE_AHDL_TDX_FILE = ON; VERILOG_NETLIST_WRITER = OFF; USE_SYNOPSYS_SYNTHESIS = OFF; SYNOPSYS_COMPILER = DESIGN; SYNOPSYS_DESIGNWARE = OFF; SYNOPSYS_HIERARCHICAL_COMPILATION = ON; SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF; SYNOPSYS_MAPPING_EFFORT = MEDIUM; VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF; VERILOG_TRUNCATE_HIERARCHY_PATH = OFF; VHDL_TRUNCATE_HIERARCHY_PATH = OFF; EDIF_TRUNCATE_HIERARCHY_PATH = OFF; VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE; VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF; EDIF_INPUT_LMF1 = *.lmf; EDIF_INPUT_LMF2 = *.lmf; EDIF_INPUT_VCC = VCC; EDIF_INPUT_GND = GND; EDIF_OUTPUT_VCC = VCC; EDIF_INPUT_USE_LMF1 = OFF; EDIF_INPUT_USE_LMF2 = OFF; EDIF_OUTPUT_USE_EDC = OFF; EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE; EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF; EDIF_FLATTEN_BUS = OFF; EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF; NETLIST_OUTPUT_TIME_SCALE = 0.1ns; EDIF_NETLIST_WRITER = ON; EDIF_OUTPUT_EDC_FILE = "e:\alexis\sumet\sumet_2\*.edc"; EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = ON; EDIF_BUS_DELIMITERS = (); VHDL_WRITER_VERSION = VHDL93; VHDL_NETLIST_WRITER = ON; EDIF_OUTPUT_VERSION = 300; EDIF_OUTPUT_GND = GND; EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF; END; CUSTOM_DESIGN_DOCTOR_RULES BEGIN RIPPLE_CLOCKS = ON; GATED_CLOCKS = ON; MULTI_LEVEL_CLOCKS = ON; MULTI_CLOCK_NETWORKS = ON; STATIC_HAZARDS_BEFORE_SYNTHESIS = ON; STATIC_HAZARDS_AFTER_SYNTHESIS = OFF; PRESET_CLEAR_NETWORKS = ON; ASYNCHRONOUS_INPUTS = ON; DELAY_CHAINS = ON; RACE_CONDITIONS = ON; EXPANDER_NETWORKS = ON; MASTER_RESET = OFF; END; SIMULATOR_CONFIGURATION BEGIN BIDIR_PIN = STRONG; END_TIME = 1.0us; SIMULATION_INPUT_FILE = vme_interface.scf; USE_DEVICE = OFF; SETUP_HOLD = OFF; CHECK_OUTPUTS = OFF; OSCILLATION = OFF; OSCILLATION_TIME = 0.0ns; GLITCH = OFF; GLITCH_TIME = 0.0ns; START_TIME = 0.0ns; END; TIMING_ANALYZER_CONFIGURATION BEGIN CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF; |valid_addr.Q : DELAY_MATRIX_DESTINATION; |valid_addr.D : DELAY_MATRIX_DESTINATION; |valid_addr.CLK : DELAY_MATRIX_DESTINATION; |_AS : DELAY_MATRIX_SOURCE; |Address31 : DELAY_MATRIX_SOURCE; |Address30 : DELAY_MATRIX_SOURCE; |Address29 : DELAY_MATRIX_SOURCE; |Address28 : DELAY_MATRIX_SOURCE; |Address27 : DELAY_MATRIX_SOURCE; ANALYSIS_MODE = DELAY_MATRIX; AUTO_RECALCULATE = OFF; CUT_OFF_IO_PIN_FEEDBACK = ON; CUT_OFF_CLEAR_AND_PRESET_PATHS = ON; LIST_ONLY_LONGEST_PATH = ON; DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS; INCLUDE_PATHS_GREATER_THAN = OFF; INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns; INCLUDE_PATHS_LESS_THAN = OFF; INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms; REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS; LIST_PATH_COUNT = 10; LIST_PATH_FREQUENCY = 10MHz; CELL_WIDTH = 20; END; OTHER_CONFIGURATION BEGIN LAST_MAXPLUS2_VERSION = 10.1; LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100; ORIGINAL_MAXPLUS2_VERSION = 8.0; ROW_PINS_PERCENT = 50; EXP_PER_LCELL_PERCENT = 100; FAN_IN_PER_LCELL_PERCENT = 100; LCELLS_PER_ROW_PERCENT = 100; DEFAULT_9K_EXP_PER_LCELL = 1/2; FLEX_10K_52_COLUMNS = 40; EXPLICIT_FAMILY = 1; NORMAL_LCELL_INSERT = ON; CARRY_OUT_PINS_LCELL_INSERT = OFF; ROW_PINS_LCELL_INSERT = ON; COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,1,1,1,1"; END; DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = ON; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = OFF; FAST_IO = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = ON; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = ON; SUBFACTOR_EXTRACTION = ON; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = ON; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = OFF; FAST_IO = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = ON; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = ON; SUBFACTOR_EXTRACTION = ON; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = OFF; FAST_IO = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = 2; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = 32; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = ON; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = ON; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = ON; SUBFACTOR_EXTRACTION = ON; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000 BEGIN CASCADE_CHAIN = IGNORE; CARRY_CHAIN = IGNORE; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = ON; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = OFF; FAST_IO = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000 BEGIN CASCADE_CHAIN = IGNORE; CARRY_CHAIN = IGNORE; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = ON; TURBO_BIT = ON; PARALLEL_EXPANDERS = ON; IGNORE_SOFT_BUFFERS = OFF; FAST_IO = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC BEGIN CASCADE_CHAIN = IGNORE; CARRY_CHAIN = IGNORE; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = OFF; FAST_IO = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000 BEGIN CASCADE_CHAIN = AUTO; CASCADE_CHAIN_LENGTH = 2; CARRY_CHAIN = AUTO; CARRY_CHAIN_LENGTH = 32; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; MINIMIZATION = PARTIAL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = OFF; FAST_IO = OFF; SOFT_BUFFER_INSERTION = OFF; DECOMPOSE_GATES = OFF; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = OFF; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; MINIMIZATION = PARTIAL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = OFF; FAST_IO = OFF; SOFT_BUFFER_INSERTION = OFF; DECOMPOSE_GATES = OFF; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = OFF; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; MINIMIZATION = PARTIAL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = OFF; FAST_IO = OFF; SOFT_BUFFER_INSERTION = OFF; DECOMPOSE_GATES = ON; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000 BEGIN CASCADE_CHAIN = MANUAL; CASCADE_CHAIN_LENGTH = 2; CARRY_CHAIN = MANUAL; CARRY_CHAIN_LENGTH = 32; MINIMIZATION = PARTIAL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = ON; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = OFF; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = OFF; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE withSOFT.MAX5000 BEGIN SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = ON; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; USE_LPM_FOR_AHDL_OPERATORS = OFF; IGNORE_SOFT_BUFFERS = OFF; FAST_IO = OFF; MINIMIZATION = FULL; CASCADE_CHAIN = IGNORE; CARRY_CHAIN = IGNORE; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = ON; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = ON; SUBFACTOR_EXTRACTION = ON; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; REGISTER_OPTIMIZATION = ON; CLKLOCKX1_INPUT_FREQ = 0.00; END; DEFINE_LOGIC_SYNTHESIS_STYLE withSOFT.MAX7000 BEGIN SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = ON; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; USE_LPM_FOR_AHDL_OPERATORS = OFF; IGNORE_SOFT_BUFFERS = OFF; FAST_IO = OFF; MINIMIZATION = FULL; CASCADE_CHAIN = IGNORE; CARRY_CHAIN = IGNORE; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = ON; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = ON; SUBFACTOR_EXTRACTION = ON; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; REGISTER_OPTIMIZATION = ON; CLKLOCKX1_INPUT_FREQ = 0.00; END; DEFINE_LOGIC_SYNTHESIS_STYLE withSOFT.CLASSIC BEGIN SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; USE_LPM_FOR_AHDL_OPERATORS = OFF; IGNORE_SOFT_BUFFERS = OFF; FAST_IO = OFF; MINIMIZATION = FULL; CASCADE_CHAIN = IGNORE; CARRY_CHAIN = IGNORE; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = ON; REGISTER_OPTIMIZATION = OFF; CLKLOCKX1_INPUT_FREQ = 0.00; END; DEFINE_LOGIC_SYNTHESIS_STYLE withSOFT.FLEX8000 BEGIN SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; USE_LPM_FOR_AHDL_OPERATORS = OFF; MINIMIZATION = FULL; CASCADE_CHAIN = IGNORE; CARRY_CHAIN = IGNORE; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = ON; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = ON; SUBFACTOR_EXTRACTION = ON; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; REGISTER_OPTIMIZATION = ON; CASCADE_CHAIN_LENGTH = 2; CARRY_CHAIN_LENGTH = 32; END;