Changes to HF PCB for production

• Changed EPC1 to EPC2. EPC1 is a write-once PROM that requires special hardware to burn. EPC2 is a FRAM-based device that can be reprogrammed in situ via JTAG.
  
  
• Added JTAG access to all Altera chips. This allows for the possibility of using boundary-scan testing to find connection problems. We now have the following JTAG chains. (Note that FP4,5,6 are on PCB surface, not front panel. TP are test points.)
  
  
  • FP2(TDI) - EPC2(U109) - Boot(U84) - FP2(TDO)
  • FP3(TDI) - Merger(U101) - FP3(TDO)
  • FP4(TDI) - DAD0(U91) - TP12 - DAD1(U92) - TP11 - MOP(U30) - FP4(TDO)
  • FP5(TDI) - HM0(U41) - TP13 - HM6(U40) - TP14 - HM2(U39) - TP15 - HM8(U38) - TP16 - HM4(U37) - FP5(TDO)
  • FP6(TDI) - HM5(U36) - TP17 - HM1(U35) - TP18 - HM7(U34) - TP19 - HM3(U33) - TP20 - HM9(U32) - FP6(TDO)
  
  
  
• Added pullups to VCC on CONF_DONE and nSTATUS members of main Flex configuration chain (MOP + 10*HitMan + 2*DAD). We can't configure the board without them.
  
  
• Made pin changes on HitMan chip. Main reason is to eliminate skew between clock and data entering chip from DAD, which was about 10 nsec.
  
  
  • Moved dadclock from AA22 to AF13 (uses global clock for signal whose timing is critical)
  • Moved hf_init from AF13 to W23 (frees global clock for dadclock)
  • Moved vmeaddr0 from B14 to AE11 (frees dedicated input for internal use)
  • Moved vmeaddr1 from AE13 to AF24 (frees dedicated input for internal use)
  • Moved vmeaddr2 from A13 to AE4 (frees dedicated input for internal use)
  • Moved vmeclock from A14 to AA22 (frees global clock for internal use)
  
  
  
• Added pulldown to ground on FRAM RP* (reset/power-down) pin. This prevents memory corruption when +3.3V fails (or comes up later than 5V when cycling power).
  
  
• Changed FRAM VPEN pin to O/C output from Boot chip, with pullup to 5V. A simple output from Boot chip won't work, as voltage > 4.5 is required to enable programming, and Boot obviously can't drive outputs above 3.3.
  
  
• Power LED now checks both supply voltages (3.3 and 5). Use of the wrong symbol in the schematic made prototype check only 5.
  
  
• Fixed bug in LED control logic. Affects LEDs in which (active-low) signal is OR'ed with (active-low) one-shot output: IntError, Error, DS, Hold. Prototype misapplied DeMorgan's law and used NAND instead of AND as active-low OR.
  
  
• Routed Hold LED logic through MOP chip, for added flexibility.
  
  
• Moved LEDs back from front panel for better clearance.