--
--  Copyright (C) 1988-2001 Altera Corporation
--  Any megafunction design, and related net list (encrypted or decrypted),
--  support information, device programming or simulation file, and any other
--  associated documentation or information provided by Altera or a partner
--  under Altera's Megafunction Partnership Program may be used only to
--  program PLD devices (but not masked PLD devices) from Altera.  Any other
--  use of such megafunction design, net list, support information, device
--  programming or simulation file, or any other related documentation or
--  information is prohibited for any other purpose, including, but not
--  limited to modification, reverse engineering, de-compiling, or use with
--  any other silicon devices, unless such use is explicitly licensed under
--  a separate agreement with Altera or a megafunction partner.  Title to
--  the intellectual property, including patents, copyrights, trademarks,
--  trade secrets, or maskworks, embodied in any such megafunction design,
--  net list, support information, device programming or simulation file, or
--  any other related documentation or information provided by Altera or a
--  megafunction partner, remains with Altera, the megafunction partner, or
--  their respective licensors.  No other licenses, including any licenses
--  needed under any third party's intellectual property, are provided herein.
--
CHIP boot
BEGIN
	|framvpen :	BIDIR_PIN = Y4;
	|MOP_Spare4 :	OUTPUT_PIN = K23;
	|MOP_Spare3 :	OUTPUT_PIN = J25;
	|MOP_Spare2 :	OUTPUT_PIN = J3;
	|MOP_Spare1 :	OUTPUT_PIN = H26;
	|MOP_Spare0 :	OUTPUT_PIN = J2;
	|INIT_DELIN :	OUTPUT_PIN = C1;
	|INIT_DELOUT :	INPUT_PIN = E5;
	|_DTACK :	BIDIR_PIN = AD24;
	|_BERR :	BIDIR_PIN = R24;
	|vmedata31 :	BIDIR_PIN = J22;
	|vmedata30 :	BIDIR_PIN = W4;
	|vmedata29 :	BIDIR_PIN = W24;
	|vmedata28 :	BIDIR_PIN = V1;
	|vmedata27 :	BIDIR_PIN = V23;
	|vmedata26 :	BIDIR_PIN = V5;
	|vmedata25 :	BIDIR_PIN = W26;
	|vmedata24 :	BIDIR_PIN = V4;
	|vmedata23 :	BIDIR_PIN = V22;
	|vmedata22 :	BIDIR_PIN = W2;
	|vmedata21 :	BIDIR_PIN = W25;
	|vmedata20 :	BIDIR_PIN = W3;
	|vmedata19 :	BIDIR_PIN = K26;
	|vmedata18 :	BIDIR_PIN = H25;
	|vmedata17 :	BIDIR_PIN = V24;
	|vmedata16 :	BIDIR_PIN = V25;
	|vmedata15 :	BIDIR_PIN = Y3;
	|vmedata14 :	BIDIR_PIN = B20;
	|vmedata13 :	BIDIR_PIN = AE23;
	|vmedata12 :	BIDIR_PIN = AE21;
	|vmedata11 :	BIDIR_PIN = AE20;
	|vmedata10 :	BIDIR_PIN = A24;
	|vmedata9 :	BIDIR_PIN = L23;
	|vmedata8 :	BIDIR_PIN = C23;
	|vmedata7 :	BIDIR_PIN = AE19;
	|vmedata6 :	BIDIR_PIN = B21;
	|vmedata5 :	BIDIR_PIN = AE24;
	|vmedata4 :	BIDIR_PIN = AD21;
	|vmedata3 :	BIDIR_PIN = B23;
	|vmedata2 :	BIDIR_PIN = F25;
	|vmedata1 :	BIDIR_PIN = J23;
	|vmedata0 :	BIDIR_PIN = C20;
	|HF_VME_Data31 :	BIDIR_PIN = H2;
	|HF_VME_Data30 :	BIDIR_PIN = C17;
	|HF_VME_Data29 :	BIDIR_PIN = A21;
	|HF_VME_Data28 :	BIDIR_PIN = AD6;
	|HF_VME_Data27 :	BIDIR_PIN = A3;
	|HF_VME_Data26 :	BIDIR_PIN = AE18;
	|HF_VME_Data25 :	BIDIR_PIN = AE22;
	|HF_VME_Data24 :	BIDIR_PIN = AF24;
	|HF_VME_Data23 :	BIDIR_PIN = AD7;
	|HF_VME_Data22 :	BIDIR_PIN = AE4;
	|HF_VME_Data21 :	BIDIR_PIN = B3;
	|HF_VME_Data20 :	BIDIR_PIN = Y1;
	|HF_VME_Data19 :	BIDIR_PIN = J5;
	|HF_VME_Data18 :	BIDIR_PIN = J4;
	|HF_VME_Data17 :	BIDIR_PIN = V3;
	|HF_VME_Data16 :	BIDIR_PIN = W23;
	|HF_VME_Data15 :	BIDIR_PIN = B19;
	|HF_VME_Data14 :	BIDIR_PIN = B17;
	|HF_VME_Data13 :	BIDIR_PIN = AE17;
	|HF_VME_Data12 :	BIDIR_PIN = A18;
	|HF_VME_Data11 :	BIDIR_PIN = AA23;
	|HF_VME_Data10 :	BIDIR_PIN = D26;
	|HF_VME_Data9 :	BIDIR_PIN = B6;
	|HF_VME_Data8 :	BIDIR_PIN = AB4;
	|HF_VME_Data7 :	BIDIR_PIN = AC1;
	|HF_VME_Data6 :	BIDIR_PIN = AE3;
	|HF_VME_Data5 :	BIDIR_PIN = C4;
	|HF_VME_Data4 :	BIDIR_PIN = AD15;
	|HF_VME_Data3 :	BIDIR_PIN = P23;
	|HF_VME_Data2 :	BIDIR_PIN = AB26;
	|HF_VME_Data1 :	BIDIR_PIN = A16;
	|HF_VME_Data0 :	BIDIR_PIN = G23;
	|framdata15 :	BIDIR_PIN = AA2;
	|framdata14 :	BIDIR_PIN = C16;
	|framdata13 :	BIDIR_PIN = AD16;
	|framdata12 :	BIDIR_PIN = B16;
	|framdata11 :	BIDIR_PIN = AF17;
	|framdata10 :	BIDIR_PIN = A15;
	|framdata9 :	BIDIR_PIN = AD9;
	|framdata8 :	BIDIR_PIN = AD5;
	|framdata7 :	BIDIR_PIN = AD4;
	|framdata6 :	BIDIR_PIN = C3;
	|framdata4 :	BIDIR_PIN = AE16;
	|framdata3 :	BIDIR_PIN = A17;
	|framdata2 :	BIDIR_PIN = B15;
	|framdata1 :	BIDIR_PIN = AE15;
	|framdata0 :	BIDIR_PIN = AF15;
	|VTM_Serial :	BIDIR_PIN = AB3;
	|dir_trans :	OUTPUT_PIN = U24;
	|_MODSEL :	OUTPUT_PIN = AD19;
	|_vme_data_str :	OUTPUT_PIN = AA25;
	|dsdelayin :	OUTPUT_PIN = M25;
	|HF_VME_Addr24 :	OUTPUT_PIN = N4;
	|HF_VME_Addr23 :	OUTPUT_PIN = M24;
	|HF_VME_Addr22 :	OUTPUT_PIN = M5;
	|HF_VME_Addr21 :	OUTPUT_PIN = N2;
	|HF_VME_Addr20 :	OUTPUT_PIN = M4;
	|HF_VME_Addr19 :	OUTPUT_PIN = AF10;
	|HF_VME_Addr18 :	OUTPUT_PIN = M2;
	|HF_VME_Addr17 :	OUTPUT_PIN = L25;
	|HF_VME_Addr16 :	OUTPUT_PIN = L26;
	|HF_VME_Addr15 :	OUTPUT_PIN = L3;
	|HF_VME_Addr14 :	OUTPUT_PIN = K4;
	|HF_VME_Addr13 :	OUTPUT_PIN = L2;
	|HF_VME_Addr12 :	OUTPUT_PIN = K3;
	|HF_VME_Addr11 :	OUTPUT_PIN = K2;
	|HF_VME_Addr10 :	OUTPUT_PIN = L1;
	|HF_VME_Addr9 :	OUTPUT_PIN = L5;
	|HF_VME_Addr8 :	OUTPUT_PIN = K25;
	|HF_VME_Addr7 :	OUTPUT_PIN = L22;
	|HF_VME_Addr6 :	OUTPUT_PIN = L24;
	|HF_VME_Addr5 :	OUTPUT_PIN = G5;
	|HF_VME_Addr4 :	OUTPUT_PIN = F3;
	|HF_VME_Addr3 :	OUTPUT_PIN = K24;
	|HF_VME_Addr2 :	OUTPUT_PIN = F2;
	|HF_VME_Addr1 :	OUTPUT_PIN = G4;
	|HF_VME_Addr0 :	OUTPUT_PIN = AF8;
	|HF_VME_AS :	OUTPUT_PIN = Y25;
	|HF_VME_DS :	OUTPUT_PIN = E25;
	|HF_VME_Write :	OUTPUT_PIN = M22;
	|HF_VME_Spare :	OUTPUT_PIN = AD1;
	|framaddress20 :	OUTPUT_PIN = T23;
	|framaddress19 :	OUTPUT_PIN = AB23;
	|framaddress18 :	OUTPUT_PIN = AC4;
	|framaddress17 :	OUTPUT_PIN = Y23;
	|framaddress16 :	OUTPUT_PIN = J24;
	|framaddress15 :	OUTPUT_PIN = Y5;
	|framaddress14 :	OUTPUT_PIN = AA4;
	|framaddress13 :	OUTPUT_PIN = N25;
	|framaddress12 :	OUTPUT_PIN = D1;
	|framaddress11 :	OUTPUT_PIN = E22;
	|framaddress10 :	OUTPUT_PIN = E26;
	|framaddress9 :	OUTPUT_PIN = AA24;
	|framaddress8 :	OUTPUT_PIN = AC26;
	|framaddress7 :	OUTPUT_PIN = Y24;
	|framaddress6 :	OUTPUT_PIN = E23;
	|framaddress5 :	OUTPUT_PIN = F5;
	|framaddress4 :	OUTPUT_PIN = AA22;
	|framaddress3 :	OUTPUT_PIN = U3;
	|framaddress2 :	OUTPUT_PIN = E24;
	|framaddress1 :	OUTPUT_PIN = U4;
	|framaddress0 :	OUTPUT_PIN = U22;
	|framoe_ :	OUTPUT_PIN = T24;
	|framwe_ :	OUTPUT_PIN = F22;
	|framce_ :	OUTPUT_PIN = U23;
	|framrp_ :	OUTPUT_PIN = Y2;
	|nCONFIG :	OUTPUT_PIN = AB25;
	|DATA0 :	OUTPUT_PIN = T22;
	|VALID :	OUTPUT_PIN = G1;
	|DCLK :	OUTPUT_PIN = AA26;
	|CONF_DONE_bkup :	OUTPUT_PIN = U1;
	|nSTATUS_bkup :	OUTPUT_PIN = A12;
	|SVT_ERROR_ :	OUTPUT_PIN = AD12;
	|SVT_LostLock_ :	OUTPUT_PIN = E4;
	|CDF_ERROR_ :	OUTPUT_PIN = AF12;
	|VTM_Reset :	OUTPUT_PIN = AA5;
	|MOP_TestClock :	OUTPUT_PIN = T2;
	|Merger_Clock :	OUTPUT_PIN = N5;
	|HM9_TestClock :	OUTPUT_PIN = W5;
	|HM8_TestClock :	OUTPUT_PIN = T5;
	|HM7_TestClock :	OUTPUT_PIN = U2;
	|HM6_TestClock :	OUTPUT_PIN = E1;
	|HM5_TestClock :	OUTPUT_PIN = A11;
	|HM4_TestClock :	OUTPUT_PIN = AE12;
	|HM3_TestClock :	OUTPUT_PIN = AD13;
	|HM2_TestClock :	OUTPUT_PIN = T3;
	|HM1_TestClock :	OUTPUT_PIN = AE11;
	|HM0_TestClock :	OUTPUT_PIN = AB2;
	|HF_Test2 :	OUTPUT_PIN = U25;
	|HF_Test1 :	OUTPUT_PIN = H3;
	|HF_Test0 :	OUTPUT_PIN = V26;
	|HF_Spare :	OUTPUT_PIN = Y22;
	|HF_Init :	OUTPUT_PIN = AB22;
	|HF_Freeze :	OUTPUT_PIN = K22;
	|HF_Load :	OUTPUT_PIN = T4;
	|Test_LED :	OUTPUT_PIN = AA3;
	|Load_LED :	OUTPUT_PIN = M3;
	|Boot_LED :	OUTPUT_PIN = AB5;
	|Error_LED :	OUTPUT_PIN = Y26;
	|IntError_LED :	OUTPUT_PIN = L4;
	|Run_LED :	OUTPUT_PIN = E2;
	|Ack_LED :	OUTPUT_PIN = AB24;
	|nCONFIG_bkup :	INPUT_PIN = G24;
	|DATA0_bkup :	INPUT_PIN = AE8;
	|DCLK_bkup :	INPUT_PIN = AF5;
	|address28 :	INPUT_PIN = P3;
	|_GA1 :	INPUT_PIN = R5;
	|address29 :	INPUT_PIN = C22;
	|_GA2 :	INPUT_PIN = P5;
	|address31 :	INPUT_PIN = A4;
	|_GA4 :	INPUT_PIN = R2;
	|address27 :	INPUT_PIN = P1;
	|_GA0 :	INPUT_PIN = P22;
	|address30 :	INPUT_PIN = AE6;
	|_GA3 :	INPUT_PIN = P4;
	|_LWORD :	INPUT_PIN = B8;
	|_AS :	INPUT_PIN = AF13;
	|_IACK :	INPUT_PIN = AF6;
	|_DS1 :	INPUT_PIN = AF23;
	|_DS0 :	INPUT_PIN = C24;
	|_vme_write :	INPUT_PIN = A19;
	|CONF_DONE :	INPUT_PIN = AF9;
	|nSTATUS :	INPUT_PIN = C8;
	|HF_SVTerror :	INPUT_PIN = C7;
	|HF_LostLock :	INPUT_PIN = B2;
	|HF_CDFerror :	INPUT_PIN = AF22;
	|HF_Clock :	INPUT_PIN = AF20;
	|dsdelayout5 :	INPUT_PIN = AE13;
	|AM0 :	INPUT_PIN = P25;
	|SVT_FREEZE_ :	INPUT_PIN = C21;
	|address26 :	INPUT_PIN = N24;
	|address25 :	INPUT_PIN = P26;
	|address24 :	INPUT_PIN = N23;
	|address23 :	INPUT_PIN = N22;
	|address22 :	INPUT_PIN = A9;
	|address21 :	INPUT_PIN = G25;
	|address20 :	INPUT_PIN = AF2;
	|address19 :	INPUT_PIN = B24;
	|address18 :	INPUT_PIN = AE5;
	|address17 :	INPUT_PIN = C6;
	|address16 :	INPUT_PIN = B18;
	|address15 :	INPUT_PIN = AF21;
	|address14 :	INPUT_PIN = B5;
	|address13 :	INPUT_PIN = AF18;
	|address12 :	INPUT_PIN = C10;
	|address11 :	INPUT_PIN = AF4;
	|address10 :	INPUT_PIN = AD22;
	|address9 :	INPUT_PIN = A22;
	|address8 :	INPUT_PIN = C19;
	|address7 :	INPUT_PIN = F24;
	|address6 :	INPUT_PIN = H5;
	|address5 :	INPUT_PIN = F26;
	|address4 :	INPUT_PIN = G22;
	|address3 :	INPUT_PIN = G26;
	|address2 :	INPUT_PIN = G2;
	|_delayed_modsel :	INPUT_PIN = G3;
	|framsts :	INPUT_PIN = P24;
	|dsdelayout9 :	INPUT_PIN = C12;
	|dsdelayout8 :	INPUT_PIN = B10;
	|dsdelayout1 :	INPUT_PIN = A13;
	|dsdelayout6 :	INPUT_PIN = AF14;
	|dsdelayout3 :	INPUT_PIN = B14;
	|SVT_INIT_ :	INPUT_PIN = R3;
	|dsdelayout0 :	INPUT_PIN = C18;
	|dsdelayout7 :	INPUT_PIN = AD10;
	|AM2 :	INPUT_PIN = AD23;
	|dsdelayout4 :	INPUT_PIN = B7;
	|dsdelayout2 :	INPUT_PIN = R23;
	|AM3 :	INPUT_PIN = R4;
	|AM1 :	INPUT_PIN = AD17;
	|AM4 :	INPUT_PIN = R25;
	|AM5 :	INPUT_PIN = R22;
	|Merger_Spare :	INPUT_PIN = B9;
	|HM9_Spare :	INPUT_PIN = B11;
	|HM8_Spare :	INPUT_PIN = AD8;
	|HM7_Spare :	INPUT_PIN = C11;
	|HM6_Spare :	INPUT_PIN = A6;
	|HM5_Spare :	INPUT_PIN = A5;
	|HM4_Spare :	INPUT_PIN = AE9;
	|HM3_Spare :	INPUT_PIN = A8;
	|HM2_Spare :	INPUT_PIN = AE10;
	|HM1_Spare :	INPUT_PIN = AD11;
	|HM0_Spare :	INPUT_PIN = B12;
	|DAD1_Spare :	OUTPUT_PIN = H4;
	|DAD0_Spare :	OUTPUT_PIN = H1;
	|SVT_SPARE_ :	INPUT_PIN = A25;
	|framdata5 :	BIDIR_PIN = C5;
	|_delayed_DS :	INPUT_PIN = A14;
	DEVICE = EPF10K50VBC356-2;
END;

DEFAULT_DEVICES
BEGIN
	AUTO_DEVICE = EPF10K100ABC600-1;
	AUTO_DEVICE = EPF10K100AFC484-1;
	AUTO_DEVICE = EPF10K100ABC356-1;
	AUTO_DEVICE = EPF10K100ARC240-1;
	AUTO_DEVICE = EPF10K50VBC356-1;
	AUTO_DEVICE = EPF10K50VRC240-1;
	AUTO_DEVICE = EPF10K30AFC484-1;
	AUTO_DEVICE = EPF10K30ABC356-1;
	AUTO_DEVICE = EPF10K30AFC256-1;
	AUTO_DEVICE = EPF10K30AQC240-1;
	AUTO_DEVICE = EPF10K30AQC208-1;
	AUTO_DEVICE = EPF10K30ATC144-1;
	AUTO_DEVICE = EPF10K10AFC256-1;
	AUTO_DEVICE = EPF10K10AQC208-1;
	AUTO_DEVICE = EPF10K10ATC144-1;
	AUTO_DEVICE = EPF10K10ATC100-1;
	ASK_BEFORE_ADDING_EXTRA_DEVICES = ON;
END;

TIMING_POINT
BEGIN
	MAINTAIN_STABLE_SYNTHESIS = ON;
	DEVICE_FOR_TIMING_SYNTHESIS = EPF10K50VBC356-2;
	CUT_ALL_CLEAR_PRESET = ON;
	CUT_ALL_BIDIR = ON;
END;

IGNORED_ASSIGNMENTS
BEGIN
	IGNORE_PIN_ASSIGNMENTS = OFF;
	DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF;
	IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF;
	IGNORE_DEVICE_ASSIGNMENTS = OFF;
	IGNORE_LC_ASSIGNMENTS = OFF;
	IGNORE_CHIP_ASSIGNMENTS = OFF;
	IGNORE_TIMING_ASSIGNMENTS = OFF;
	IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF;
	IGNORE_CLIQUE_ASSIGNMENTS = OFF;
	FIT_IGNORE_TIMING = OFF;
END;

LOGIC_OPTIONS
BEGIN
	|hf_vme_data31 :	SLOW_SLEW_RATE = ON;
	|hf_vme_data30 :	SLOW_SLEW_RATE = ON;
	|hf_vme_data29 :	SLOW_SLEW_RATE = ON;
	|hf_vme_data28 :	SLOW_SLEW_RATE = ON;
	|hf_vme_data27 :	SLOW_SLEW_RATE = ON;
	|hf_vme_data26 :	SLOW_SLEW_RATE = ON;
	|hf_vme_data25 :	SLOW_SLEW_RATE = ON;
	|hf_vme_data24 :	SLOW_SLEW_RATE = ON;
	|hf_vme_data23 :	SLOW_SLEW_RATE = ON;
	|hf_vme_data22 :	SLOW_SLEW_RATE = ON;
	|hf_vme_data21 :	SLOW_SLEW_RATE = ON;
	|hf_vme_data20 :	SLOW_SLEW_RATE = ON;
	|hf_vme_data19 :	SLOW_SLEW_RATE = ON;
	|hf_vme_data18 :	SLOW_SLEW_RATE = ON;
	|hf_vme_data17 :	SLOW_SLEW_RATE = ON;
	|hf_vme_data16 :	SLOW_SLEW_RATE = ON;
	|hf_vme_data15 :	SLOW_SLEW_RATE = ON;
	|hf_vme_data14 :	SLOW_SLEW_RATE = ON;
	|hf_vme_data13 :	SLOW_SLEW_RATE = ON;
	|hf_vme_data12 :	SLOW_SLEW_RATE = ON;
	|hf_vme_data11 :	SLOW_SLEW_RATE = ON;
	|hf_vme_data10 :	SLOW_SLEW_RATE = ON;
	|hf_vme_data9 :	SLOW_SLEW_RATE = ON;
	|hf_vme_data8 :	SLOW_SLEW_RATE = ON;
	|hf_vme_data7 :	SLOW_SLEW_RATE = ON;
	|hf_vme_data6 :	SLOW_SLEW_RATE = ON;
	|hf_vme_data5 :	SLOW_SLEW_RATE = ON;
	|hf_vme_data4 :	SLOW_SLEW_RATE = ON;
	|hf_vme_data3 :	SLOW_SLEW_RATE = ON;
	|hf_vme_data2 :	SLOW_SLEW_RATE = ON;
	|hf_vme_data1 :	SLOW_SLEW_RATE = ON;
	|hf_vme_data0 :	SLOW_SLEW_RATE = ON;
END;

GLOBAL_PROJECT_DEVICE_OPTIONS
BEGIN
	FLEX_CONFIGURATION_EPROM = EPC2LC20;
	MAX7000B_ENABLE_VREFB = OFF;
	MAX7000B_ENABLE_VREFA = OFF;
	MAX7000B_VCCIO_IOBANK2 = 3.3V;
	MAX7000B_VCCIO_IOBANK1 = 3.3V;
	CONFIG_EPROM_PULLUP_RESISTOR = ON;
	CONFIG_EPROM_USER_CODE = FFFFFFFF;
	ENABLE_CHIP_WIDE_OE = ON;
	MULTIVOLT_IO = OFF;
	FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
	FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON;
	FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
	FLEX6000_ENABLE_JTAG = OFF;
	CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL;
	MAX7000S_ENABLE_JTAG = ON;
	FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
	MAX7000S_USER_CODE = FFFF;
	CONFIG_SCHEME_10K = PASSIVE_SERIAL;
	FLEX10K_JTAG_USER_CODE = 7F;
	ENABLE_INIT_DONE_OUTPUT = OFF;
	ENABLE_CHIP_WIDE_RESET = OFF;
	nCEO = UNRESERVED;
	CLKUSR = UNRESERVED;
	ADD17 = UNRESERVED;
	ADD16 = UNRESERVED;
	ADD15 = UNRESERVED;
	ADD14 = UNRESERVED;
	ADD13 = UNRESERVED;
	ADD0_TO_ADD12 = UNRESERVED;
	SDOUT = RESERVED_DRIVES_OUT;
	RDCLK = UNRESERVED;
	RDYnBUSY = UNRESERVED;
	nWS_nRS_nCS_CS = UNRESERVED;
	DATA1_TO_DATA7 = UNRESERVED;
	DATA0 = RESERVED_TRI_STATED;
	FLEX8000_ENABLE_JTAG = OFF;
	CONFIG_SCHEME = ACTIVE_SERIAL;
	DISABLE_TIME_OUT = OFF;
	ENABLE_DCLK_OUTPUT = OFF;
	RELEASE_CLEARS = OFF;
	AUTO_RESTART = OFF;
	USER_CLOCK = OFF;
	SECURITY_BIT = OFF;
	RESERVED_PINS_PERCENT = 0;
	RESERVED_LCELLS_PERCENT = 0;
	MAX7000AE_USER_CODE = FFFFFFFF;
	MAX7000AE_ENABLE_JTAG = ON;
END;

GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS
BEGIN
	AUTO_IMPLEMENT_IN_EAB = ON;
	MULTI_LEVEL_SYNTHESIS_MAX9000 = OFF;
	DEVICE_FAMILY = FLEX10KA;
	OPTIMIZE_FOR_SPEED = 10;
	STYLE = NORMAL;
	AUTO_REGISTER_PACKING = ON;
	AUTO_FAST_IO = ON;
	AUTO_OPEN_DRAIN_PINS = ON;
	AUTO_GLOBAL_OE = ON;
	AUTO_GLOBAL_CLOCK = ON;
	AUTO_GLOBAL_PRESET = OFF;
	AUTO_GLOBAL_CLEAR = OFF;
	ONE_HOT_STATE_MACHINE_ENCODING = OFF;
	MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF;
END;

COMPILER_PROCESSING_CONFIGURATION
BEGIN
	OPTIMIZE_TIMING_SNF = ON;
	PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF;
	FITTER_SETTINGS = NORMAL;
	GENERATE_AHDL_TDO_FILE = OFF;
	RPT_FILE_USER_ASSIGNMENTS = ON;
	RPT_FILE_LCELL_INTERCONNECT = ON;
	RPT_FILE_HIERARCHY = ON;
	RPT_FILE_EQUATIONS = ON;
	LINKED_SNF_EXTRACTOR = OFF;
	TIMING_SNF_EXTRACTOR = ON;
	FUNCTIONAL_SNF_EXTRACTOR = OFF;
	DESIGN_DOCTOR_RULES = EPLD;
	DESIGN_DOCTOR = OFF;
	SMART_RECOMPILE = ON;
END;

COMPILER_INTERFACES_CONFIGURATION
BEGIN
	EDIF_OUTPUT_VERSION = 300;
	EDIF_BUS_DELIMITERS = ();
	EDIF_FLATTEN_BUS = OFF;
	EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
	EDIF_OUTPUT_EDC_FILE = /net/user/users/ashmansk/altera/boot/*.edc;
	EDIF_NETLIST_WRITER = ON;
	VHDL_WRITER_VERSION = VHDL87;
	VHDL_READER_VERSION = VHDL87;
	SYNOPSYS_MAPPING_EFFORT = MEDIUM;
	SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF;
	SYNOPSYS_HIERARCHICAL_COMPILATION = ON;
	SYNOPSYS_DESIGNWARE = OFF;
	SYNOPSYS_COMPILER = DESIGN;
	VHDL_NETLIST_WRITER = OFF;
	VERILOG_NETLIST_WRITER = OFF;
	XNF_GENERATE_AHDL_TDX_FILE = ON;
	XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON;
	XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC;
	VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
	VERILOG_TRUNCATE_HIERARCHY_PATH = OFF;
	VHDL_TRUNCATE_HIERARCHY_PATH = OFF;
	EDIF_TRUNCATE_HIERARCHY_PATH = OFF;
	VERILOG_FLATTEN_BUS = OFF;
	VHDL_FLATTEN_BUS = OFF;
	VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE;
	VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE;
	VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF;
	EDIF_INPUT_LMF1 = exemplar.lmf;
	EDIF_INPUT_LMF2 = *.lmf;
	EDIF_INPUT_VCC = VCC;
	EDIF_INPUT_GND = GND;
	EDIF_OUTPUT_VCC = VCC;
	EDIF_OUTPUT_GND = GND;
	EDIF_INPUT_USE_LMF1 = ON;
	EDIF_INPUT_USE_LMF2 = OFF;
	EDIF_OUTPUT_USE_EDC = OFF;
	EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE;
	EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = ON;
	EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF;
	EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = ON;
	NETLIST_OUTPUT_TIME_SCALE = 0.1ns;
	USE_SYNOPSYS_SYNTHESIS = OFF;
END;

CUSTOM_DESIGN_DOCTOR_RULES
BEGIN
	MASTER_RESET = OFF;
	EXPANDER_NETWORKS = ON;
	RACE_CONDITIONS = ON;
	DELAY_CHAINS = ON;
	ASYNCHRONOUS_INPUTS = ON;
	PRESET_CLEAR_NETWORKS = ON;
	STATIC_HAZARDS_AFTER_SYNTHESIS = OFF;
	STATIC_HAZARDS_BEFORE_SYNTHESIS = ON;
	MULTI_CLOCK_NETWORKS = ON;
	MULTI_LEVEL_CLOCKS = ON;
	GATED_CLOCKS = ON;
	RIPPLE_CLOCKS = ON;
END;

SIMULATOR_CONFIGURATION
BEGIN
	BIDIR_PIN = STRONG;
	END_TIME = 10.0us;
	START_TIME = 0.0ns;
	GLITCH_TIME = 0.0ns;
	GLITCH = OFF;
	OSCILLATION_TIME = 0.0ns;
	OSCILLATION = OFF;
	CHECK_OUTPUTS = OFF;
	USE_DEVICE = OFF;
	SETUP_HOLD = ON;
END;

TIMING_ANALYZER_CONFIGURATION
BEGIN
	ANALYSIS_MODE = DELAY_MATRIX;
	LIST_PATH_COUNT = 10;
	INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms;
	INCLUDE_PATHS_LESS_THAN = OFF;
	INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns;
	INCLUDE_PATHS_GREATER_THAN = OFF;
	CELL_WIDTH = 18;
	LIST_ONLY_LONGEST_PATH = ON;
	CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
	CUT_OFF_IO_PIN_FEEDBACK = ON;
	AUTO_RECALCULATE = OFF;
	DELAY_MATRIX_OPTIONS = SHOW_LONGEST_PATHS;
	LIST_PATH_FREQUENCY = 10.0MHz;
	REGISTERED_PERFORMANCE_OPTIONS = FREQUENCY_OF_PATHS;
	CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF;
END;

OTHER_CONFIGURATION
BEGIN
	LAST_MAXPLUS2_VERSION = 10.1;
	COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,1,1,1,1";
	FLEX_10K_52_COLUMNS = 40;
	DEFAULT_9K_EXP_PER_LCELL = 1/2;
	LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100;
	LCELLS_PER_ROW_PERCENT = 100;
	FAN_IN_PER_LCELL_PERCENT = 100;
	EXP_PER_LCELL_PERCENT = 100;
	ROW_PINS_PERCENT = 50;
	ORIGINAL_MAXPLUS2_VERSION = 8.2;
	EXPLICIT_FAMILY = 1;
	NORMAL_LCELL_INSERT = ON;
	CARRY_OUT_PINS_LCELL_INSERT = OFF;
	ROW_PINS_LCELL_INSERT = ON;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000
BEGIN
	REGISTER_OPTIMIZATION = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = ON;
	SUBFACTOR_EXTRACTION = ON;
	REFACTORIZATION = ON;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = ON;
	REDUCE_LOGIC = ON;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	FAST_IO = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = OFF;
	XOR_SYNTHESIS = ON;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = FULL;
	CARRY_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000
BEGIN
	REGISTER_OPTIMIZATION = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = ON;
	SUBFACTOR_EXTRACTION = ON;
	REFACTORIZATION = ON;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = ON;
	REDUCE_LOGIC = ON;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	FAST_IO = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = ON;
	XOR_SYNTHESIS = ON;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = FULL;
	CARRY_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC
BEGIN
	REGISTER_OPTIMIZATION = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = OFF;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	FAST_IO = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = ON;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = FULL;
	CARRY_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000
BEGIN
	REGISTER_OPTIMIZATION = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = ON;
	SUBFACTOR_EXTRACTION = ON;
	REFACTORIZATION = ON;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = ON;
	REDUCE_LOGIC = ON;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	IGNORE_SOFT_BUFFERS = ON;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = OFF;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = FULL;
	CARRY_CHAIN_LENGTH = 32;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = 2;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000
BEGIN
	REGISTER_OPTIMIZATION = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = ON;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = ON;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	FAST_IO = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = OFF;
	XOR_SYNTHESIS = ON;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = FULL;
	CARRY_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000
BEGIN
	REGISTER_OPTIMIZATION = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = ON;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = ON;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	FAST_IO = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	PARALLEL_EXPANDERS = ON;
	TURBO_BIT = ON;
	XOR_SYNTHESIS = ON;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = FULL;
	CARRY_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC
BEGIN
	REGISTER_OPTIMIZATION = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = OFF;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	FAST_IO = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = ON;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = FULL;
	CARRY_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000
BEGIN
	REGISTER_OPTIMIZATION = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = ON;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = ON;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	IGNORE_SOFT_BUFFERS = ON;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = OFF;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = FULL;
	CARRY_CHAIN_LENGTH = 32;
	CARRY_CHAIN = AUTO;
	CASCADE_CHAIN_LENGTH = 2;
	CASCADE_CHAIN = AUTO;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000
BEGIN
	REGISTER_OPTIMIZATION = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = OFF;
	MULTI_LEVEL_FACTORING = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = OFF;
	DECOMPOSE_GATES = OFF;
	SOFT_BUFFER_INSERTION = OFF;
	FAST_IO = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = OFF;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = PARTIAL;
	CARRY_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000
BEGIN
	REGISTER_OPTIMIZATION = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = OFF;
	MULTI_LEVEL_FACTORING = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = OFF;
	DECOMPOSE_GATES = OFF;
	SOFT_BUFFER_INSERTION = OFF;
	FAST_IO = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = ON;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = PARTIAL;
	CARRY_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC
BEGIN
	REGISTER_OPTIMIZATION = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = OFF;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = OFF;
	FAST_IO = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = ON;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = PARTIAL;
	CARRY_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000
BEGIN
	REGISTER_OPTIMIZATION = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = OFF;
	MULTI_LEVEL_FACTORING = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = OFF;
	DECOMPOSE_GATES = OFF;
	SOFT_BUFFER_INSERTION = ON;
	IGNORE_SOFT_BUFFERS = ON;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = OFF;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = PARTIAL;
	CARRY_CHAIN_LENGTH = 32;
	CARRY_CHAIN = MANUAL;
	CASCADE_CHAIN_LENGTH = 2;
	CASCADE_CHAIN = MANUAL;
END;