--
--  Copyright (C) 1988-2001 Altera Corporation
--  Any megafunction design, and related net list (encrypted or decrypted),
--  support information, device programming or simulation file, and any other
--  associated documentation or information provided by Altera or a partner
--  under Altera's Megafunction Partnership Program may be used only to
--  program PLD devices (but not masked PLD devices) from Altera.  Any other
--  use of such megafunction design, net list, support information, device
--  programming or simulation file, or any other related documentation or
--  information is prohibited for any other purpose, including, but not
--  limited to modification, reverse engineering, de-compiling, or use with
--  any other silicon devices, unless such use is explicitly licensed under
--  a separate agreement with Altera or a megafunction partner.  Title to
--  the intellectual property, including patents, copyrights, trademarks,
--  trade secrets, or maskworks, embodied in any such megafunction design,
--  net list, support information, device programming or simulation file, or
--  any other related documentation or information provided by Altera or a
--  megafunction partner, remains with Altera, the megafunction partner, or
--  their respective licensors.  No other licenses, including any licenses
--  needed under any third party's intellectual property, are provided herein.
--
CHIP hitman
BEGIN
	|hf_init :	INPUT_PIN = W23;
	|vmeaddress2 :	INPUT_PIN = AE4;
	|vmeaddress1 :	INPUT_PIN = AF24;
	|vmeaddress0 :	INPUT_PIN = AE11;
	|vme_as :	INPUT_PIN = C10;
	|vmeclock :	INPUT_PIN = AA22;
	|hf_load :	INPUT_PIN = C6;
	|dadclock :	INPUT_PIN = AF13;
	|vmedata17 :	BIDIR_PIN = V23;
	|vmedata16 :	BIDIR_PIN = T3;
	|vmedata15 :	BIDIR_PIN = U1;
	|vmedata14 :	BIDIR_PIN = T4;
	|vmedata13 :	BIDIR_PIN = Y5;
	|vmedata12 :	BIDIR_PIN = AA2;
	|vmedata11 :	BIDIR_PIN = L24;
	|vmedata10 :	BIDIR_PIN = V1;
	|vmedata9 :	BIDIR_PIN = N5;
	|vmedata8 :	BIDIR_PIN = V5;
	|vmedata7 :	BIDIR_PIN = W2;
	|vmedata6 :	BIDIR_PIN = V22;
	|vmedata5 :	BIDIR_PIN = C22;
	|vmedata4 :	BIDIR_PIN = G2;
	|vmedata3 :	BIDIR_PIN = AF8;
	|vmedata2 :	BIDIR_PIN = R4;
	|vmedata1 :	BIDIR_PIN = B20;
	|vmedata0 :	BIDIR_PIN = B17;
	|spyadc7 :	BIDIR_PIN = AF12;
	|spyadc6 :	BIDIR_PIN = C3;
	|spyadc5 :	BIDIR_PIN = N4;
	|spyadc4 :	BIDIR_PIN = T23;
	|spyadc3 :	BIDIR_PIN = V26;
	|spyadc2 :	BIDIR_PIN = T22;
	|spyadc1 :	BIDIR_PIN = AB25;
	|spyadc0 :	BIDIR_PIN = U23;
	|spychannel7 :	BIDIR_PIN = T24;
	|spychannel6 :	BIDIR_PIN = U22;
	|spychannel5 :	BIDIR_PIN = AA4;
	|spychannel4 :	BIDIR_PIN = Y3;
	|spychannel3 :	BIDIR_PIN = Y4;
	|spychannel2 :	BIDIR_PIN = W26;
	|spychannel1 :	BIDIR_PIN = W25;
	|spychannel0 :	BIDIR_PIN = V25;
	|spyspare1 :	BIDIR_PIN = V24;
	|spyspare0 :	BIDIR_PIN = U2;
	|cramdata7 :	BIDIR_PIN = W24;
	|cramdata6 :	BIDIR_PIN = AE19;
	|cramdata5 :	BIDIR_PIN = AD11;
	|cramdata4 :	BIDIR_PIN = C8;
	|cramdata3 :	BIDIR_PIN = AD22;
	|cramdata2 :	BIDIR_PIN = AE20;
	|cramdata1 :	BIDIR_PIN = AB24;
	|cramdata0 :	BIDIR_PIN = L4;
	|hm_spare :	OUTPUT_PIN = C19;
	|spyaddress15 :	OUTPUT_PIN = B11;
	|spyaddress14 :	OUTPUT_PIN = M2;
	|spyaddress13 :	OUTPUT_PIN = M5;
	|spyaddress12 :	OUTPUT_PIN = AD12;
	|spyaddress11 :	OUTPUT_PIN = B23;
	|spyaddress10 :	OUTPUT_PIN = M4;
	|spyaddress9 :	OUTPUT_PIN = T2;
	|spyaddress8 :	OUTPUT_PIN = W3;
	|spyaddress7 :	OUTPUT_PIN = B5;
	|spyaddress6 :	OUTPUT_PIN = N2;
	|spyaddress5 :	OUTPUT_PIN = W4;
	|spyaddress4 :	OUTPUT_PIN = AC1;
	|spyaddress3 :	OUTPUT_PIN = AE10;
	|spyaddress2 :	OUTPUT_PIN = A6;
	|spyaddress0 :	OUTPUT_PIN = AB4;
	|spyoe :	OUTPUT_PIN = N24;
	|spycs :	OUTPUT_PIN = H25;
	|spywrite :	OUTPUT_PIN = U4;
	|spyclock :	OUTPUT_PIN = AB5;
	|cramaddress16 :	OUTPUT_PIN = AA24;
	|cramaddress15 :	OUTPUT_PIN = N3;
	|cramaddress14 :	OUTPUT_PIN = P1;
	|cramaddress13 :	OUTPUT_PIN = W5;
	|cramaddress12 :	OUTPUT_PIN = R5;
	|cramaddress11 :	OUTPUT_PIN = R3;
	|cramaddress10 :	OUTPUT_PIN = H1;
	|cramaddress9 :	OUTPUT_PIN = P3;
	|cramaddress8 :	OUTPUT_PIN = P4;
	|cramaddress7 :	OUTPUT_PIN = P5;
	|cramaddress6 :	OUTPUT_PIN = R2;
	|cramaddress5 :	OUTPUT_PIN = P25;
	|cramaddress4 :	OUTPUT_PIN = P24;
	|cramaddress3 :	OUTPUT_PIN = R22;
	|cramaddress2 :	OUTPUT_PIN = P22;
	|cramaddress1 :	OUTPUT_PIN = P23;
	|cramaddress0 :	OUTPUT_PIN = K4;
	|cramcs :	OUTPUT_PIN = C1;
	|cramwrite :	OUTPUT_PIN = B6;
	|fifodata17 :	OUTPUT_PIN = K22;
	|fifodata16 :	OUTPUT_PIN = AF9;
	|fifodata15 :	OUTPUT_PIN = U24;
	|fifodata14 :	OUTPUT_PIN = N25;
	|fifodata13 :	OUTPUT_PIN = Y22;
	|fifodata12 :	OUTPUT_PIN = AA26;
	|fifodata11 :	OUTPUT_PIN = Y24;
	|fifodata10 :	OUTPUT_PIN = P26;
	|fifodata9 :	OUTPUT_PIN = L22;
	|fifodata8 :	OUTPUT_PIN = N23;
	|fifodata7 :	OUTPUT_PIN = U25;
	|fifodata6 :	OUTPUT_PIN = Y2;
	|fifodata5 :	OUTPUT_PIN = L1;
	|fifodata4 :	OUTPUT_PIN = Y23;
	|fifodata3 :	OUTPUT_PIN = AF22;
	|fifodata2 :	OUTPUT_PIN = Y26;
	|fifodata1 :	OUTPUT_PIN = AF4;
	|fifodata0 :	OUTPUT_PIN = AD13;
	|fifoclock :	OUTPUT_PIN = AD1;
	|fifowrite :	OUTPUT_PIN = A11;
	|fifo_reset :	OUTPUT_PIN = AE23;
	|hf_spare :	INPUT_PIN = AC4;
	|vmespare :	INPUT_PIN = AB26;
	|vmeaddress15 :	INPUT_PIN = AF2;
	|hf_freeze :	INPUT_PIN = AE6;
	|vmeaddress14 :	INPUT_PIN = C4;
	|vmeaddress13 :	INPUT_PIN = AE9;
	|vmeaddress12 :	INPUT_PIN = AD9;
	|vmeaddress11 :	INPUT_PIN = A3;
	|vmeaddress10 :	INPUT_PIN = B9;
	|vmeaddress9 :	INPUT_PIN = AF5;
	|vmeaddress8 :	INPUT_PIN = AE3;
	|vmeaddress7 :	INPUT_PIN = AF6;
	|vmeaddress6 :	INPUT_PIN = A4;
	|vmeaddress5 :	INPUT_PIN = A8;
	|vmeaddress4 :	INPUT_PIN = AD5;
	|vmeaddress3 :	INPUT_PIN = AD7;
	|hf_test :	INPUT_PIN = B3;
	|vmeaddress20 :	INPUT_PIN = AC26;
	|vmewrite :	INPUT_PIN = A16;
	|vmeaddress21 :	INPUT_PIN = AA23;
	|vmeaddress22 :	INPUT_PIN = AB3;
	|vmeaddress23 :	INPUT_PIN = AB2;
	|vmeaddress24 :	INPUT_PIN = AB22;
	|dadadc7 :	INPUT_PIN = AF17;
	|dadadc6 :	INPUT_PIN = AD4;
	|dadadc5 :	INPUT_PIN = AF18;
	|dadadc4 :	INPUT_PIN = AE16;
	|dadadc3 :	INPUT_PIN = A15;
	|dadadc2 :	INPUT_PIN = AD10;
	|dadadc1 :	INPUT_PIN = A18;
	|dadadc0 :	INPUT_PIN = U3;
	|dadchannel7 :	INPUT_PIN = T5;
	|dadchannel6 :	INPUT_PIN = AE5;
	|dadchannel5 :	INPUT_PIN = B2;
	|dadchannel4 :	INPUT_PIN = C5;
	|dadchannel3 :	INPUT_PIN = AD8;
	|dadchannel2 :	INPUT_PIN = B15;
	|dadchannel1 :	INPUT_PIN = B16;
	|dadchannel0 :	INPUT_PIN = AF15;
	|dav :	INPUT_PIN = AE15;
	|grterror :	INPUT_PIN = AD6;
	|testclock :	INPUT_PIN = AB23;
	|streamid0 :	INPUT_PIN = AF20;
	|streamid1 :	INPUT_PIN = A19;
	|vmeaddress16 :	INPUT_PIN = AD15;
	|vmeaddress17 :	INPUT_PIN = AE17;
	|streamid2 :	INPUT_PIN = B10;
	|streamid3 :	INPUT_PIN = C7;
	|vmeaddress18 :	INPUT_PIN = C16;
	|vmeaddress19 :	INPUT_PIN = A17;
	|spyaddress1 :	OUTPUT_PIN = AA5;
	|cramoe :	OUTPUT_PIN = B7;
	DEVICE = EPF10K50VBC356-2;
END;

DEFAULT_DEVICES
BEGIN
	AUTO_DEVICE = EPF10K100ABC600-1;
	AUTO_DEVICE = EPF10K100ABC356-1;
	AUTO_DEVICE = EPF10K100ARC240-1;
	AUTO_DEVICE = EPF10K50VBC356-1;
	AUTO_DEVICE = EPF10K50VRC240-1;
	AUTO_DEVICE = EPF10K30ABC356-1;
	AUTO_DEVICE = EPF10K30AQC240-1;
	AUTO_DEVICE = EPF10K30AQC208-1;
	AUTO_DEVICE = EPF10K30ATC144-1;
	AUTO_DEVICE = EPF10K10AQC208-1;
	AUTO_DEVICE = EPF10K10ATC144-1;
	AUTO_DEVICE = EPF10K10ATC100-1;
	ASK_BEFORE_ADDING_EXTRA_DEVICES = ON;
END;

TIMING_POINT
BEGIN
	|ppclock :	FREQUENCY = 30MHz;
	CUT_ALL_CLEAR_PRESET = ON;
	FREQUENCY = 30.0MHz;
	CUT_ALL_BIDIR = ON;
	|testclock :	FREQUENCY = 30.00MHz;
	|dadclock :	FREQUENCY = 28.00MHz;
	|vmeclock :	FREQUENCY = 5.00MHz;
	DEVICE_FOR_TIMING_SYNTHESIS = EPF10K50VBC356-2;
	MAINTAIN_STABLE_SYNTHESIS = ON;
END;

CLIQUE fire
BEGIN
	"|hmfire:fire" :	CLIQUE;
END;

CLIQUE aim
BEGIN
	"|hmaim:aim" :	CLIQUE;
END;

CLIQUE ready
BEGIN
	"|hmready:ready" :	CLIQUE;
END;

PROBES
BEGIN
	"|hmready:ready|svxdecode:svxdecoder|invaliddata" :	PROBE = invaliddata;
END;

IGNORED_ASSIGNMENTS
BEGIN
	FIT_IGNORE_TIMING = ON;
	IGNORE_TIMING_ASSIGNMENTS = OFF;
	IGNORE_PIN_ASSIGNMENTS = OFF;
	IGNORE_CLIQUE_ASSIGNMENTS = OFF;
	IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF;
	IGNORE_CHIP_ASSIGNMENTS = OFF;
	IGNORE_LC_ASSIGNMENTS = OFF;
	IGNORE_DEVICE_ASSIGNMENTS = OFF;
	IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF;
	DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF;
END;

LOGIC_OPTIONS
BEGIN
	|ppclock :	GLOBAL_SIGNAL = ON;
	|grterror :	FAST_IO = ON;
	|dadchannel7 :	FAST_IO = ON;
	|dadchannel6 :	FAST_IO = ON;
	|dadchannel5 :	FAST_IO = ON;
	|dadchannel4 :	FAST_IO = ON;
	|dadchannel3 :	FAST_IO = ON;
	|dadchannel2 :	FAST_IO = ON;
	|dadchannel1 :	FAST_IO = ON;
	|dadchannel0 :	FAST_IO = ON;
	|dav :	FAST_IO = ON;
	|dadadc7 :	FAST_IO = ON;
	|dadadc6 :	FAST_IO = ON;
	|dadadc5 :	FAST_IO = ON;
	|dadadc4 :	FAST_IO = ON;
	|dadadc3 :	FAST_IO = ON;
	|dadadc2 :	FAST_IO = ON;
	|dadadc1 :	FAST_IO = ON;
	|dadadc0 :	FAST_IO = ON;
	|cramdata5 :	FAST_IO = ON;
	|cramdata4 :	FAST_IO = ON;
	|cramdata3 :	FAST_IO = ON;
	|cramdata2 :	FAST_IO = ON;
	|cramdata1 :	FAST_IO = ON;
	|cramdata0 :	FAST_IO = ON;
	|cramaddress16 :	FAST_IO = ON;
	|cramaddress15 :	FAST_IO = ON;
	|cramaddress14 :	FAST_IO = ON;
	|cramaddress13 :	FAST_IO = ON;
	|cramaddress12 :	FAST_IO = ON;
	|cramaddress11 :	FAST_IO = ON;
	|cramaddress10 :	FAST_IO = ON;
	|cramaddress9 :	FAST_IO = ON;
	|cramaddress8 :	FAST_IO = ON;
	|cramaddress7 :	FAST_IO = ON;
	|cramaddress6 :	FAST_IO = ON;
	|cramaddress5 :	FAST_IO = ON;
	|cramaddress4 :	FAST_IO = ON;
	|cramaddress3 :	FAST_IO = ON;
	|cramaddress2 :	FAST_IO = ON;
	|cramaddress1 :	FAST_IO = ON;
	|cramaddress0 :	FAST_IO = ON;
	|vmedata0 :	SLOW_SLEW_RATE = ON;
	|vmedata1 :	SLOW_SLEW_RATE = ON;
	|vmedata2 :	SLOW_SLEW_RATE = ON;
	|vmedata3 :	SLOW_SLEW_RATE = ON;
	|vmedata4 :	SLOW_SLEW_RATE = ON;
	|vmedata5 :	SLOW_SLEW_RATE = ON;
	|vmedata6 :	SLOW_SLEW_RATE = ON;
	|vmedata7 :	SLOW_SLEW_RATE = ON;
	|vmedata8 :	SLOW_SLEW_RATE = ON;
	|vmedata9 :	SLOW_SLEW_RATE = ON;
	|vmedata10 :	SLOW_SLEW_RATE = ON;
	|vmedata11 :	SLOW_SLEW_RATE = ON;
	|vmedata12 :	SLOW_SLEW_RATE = ON;
	|vmedata13 :	SLOW_SLEW_RATE = ON;
	|vmedata14 :	SLOW_SLEW_RATE = ON;
	|vmedata15 :	SLOW_SLEW_RATE = ON;
	|vmedata16 :	SLOW_SLEW_RATE = ON;
	|vmedata17 :	SLOW_SLEW_RATE = ON;
END;

GLOBAL_PROJECT_DEVICE_OPTIONS
BEGIN
	MAX7000B_ENABLE_VREFB = OFF;
	MAX7000B_ENABLE_VREFA = OFF;
	MAX7000B_VCCIO_IOBANK2 = 3.3V;
	MAX7000B_VCCIO_IOBANK1 = 3.3V;
	CONFIG_EPROM_PULLUP_RESISTOR = ON;
	CONFIG_EPROM_USER_CODE = FFFFFFFF;
	ENABLE_CHIP_WIDE_OE = ON;
	FLEX_CONFIGURATION_EPROM = AUTO;
	MAX7000AE_ENABLE_JTAG = ON;
	MAX7000AE_USER_CODE = FFFFFFFF;
	FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
	RESERVED_LCELLS_PERCENT = 0;
	RESERVED_PINS_PERCENT = 0;
	SECURITY_BIT = OFF;
	USER_CLOCK = OFF;
	AUTO_RESTART = OFF;
	RELEASE_CLEARS = OFF;
	ENABLE_DCLK_OUTPUT = OFF;
	DISABLE_TIME_OUT = OFF;
	CONFIG_SCHEME = ACTIVE_SERIAL;
	FLEX8000_ENABLE_JTAG = OFF;
	DATA0 = RESERVED_TRI_STATED;
	DATA1_TO_DATA7 = UNRESERVED;
	nWS_nRS_nCS_CS = UNRESERVED;
	RDYnBUSY = UNRESERVED;
	RDCLK = UNRESERVED;
	SDOUT = RESERVED_DRIVES_OUT;
	ADD0_TO_ADD12 = UNRESERVED;
	ADD13 = UNRESERVED;
	ADD14 = UNRESERVED;
	ADD15 = UNRESERVED;
	ADD16 = UNRESERVED;
	ADD17 = UNRESERVED;
	CLKUSR = UNRESERVED;
	nCEO = UNRESERVED;
	ENABLE_CHIP_WIDE_RESET = OFF;
	ENABLE_INIT_DONE_OUTPUT = OFF;
	FLEX10K_JTAG_USER_CODE = 7F;
	CONFIG_SCHEME_10K = PASSIVE_SERIAL;
	MAX7000S_USER_CODE = FFFF;
	FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
	MAX7000S_ENABLE_JTAG = ON;
	MULTIVOLT_IO = OFF;
	CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL;
	FLEX6000_ENABLE_JTAG = OFF;
	FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
	FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
END;

GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS
BEGIN
	AUTO_GLOBAL_PRESET = OFF;
	AUTO_GLOBAL_CLEAR = OFF;
	STYLE = NORMAL;
	AUTO_GLOBAL_CLOCK = ON;
	AUTO_REGISTER_PACKING = ON;
	MULTI_LEVEL_SYNTHESIS_MAX9000 = OFF;
	DEVICE_FAMILY = FLEX10KA;
	AUTO_GLOBAL_OE = OFF;
	OPTIMIZE_FOR_SPEED = 10;
	AUTO_FAST_IO = ON;
	MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF;
	ONE_HOT_STATE_MACHINE_ENCODING = OFF;
	AUTO_OPEN_DRAIN_PINS = ON;
	AUTO_IMPLEMENT_IN_EAB = OFF;
END;

COMPILER_PROCESSING_CONFIGURATION
BEGIN
	FITTER_SETTINGS = CUSTOM;
	OPTIMIZE_TIMING_SNF = ON;
	FUNCTIONAL_SNF_EXTRACTOR = OFF;
	DESIGN_DOCTOR_RULES = FLEX;
	PRESERVE_ALL_NODE_NAME_SYNONYMS = ON;
	SMART_RECOMPILE = ON;
	DESIGN_DOCTOR = OFF;
	TIMING_SNF_EXTRACTOR = ON;
	LINKED_SNF_EXTRACTOR = OFF;
	RPT_FILE_EQUATIONS = ON;
	RPT_FILE_HIERARCHY = ON;
	RPT_FILE_LCELL_INTERCONNECT = ON;
	RPT_FILE_USER_ASSIGNMENTS = ON;
	GENERATE_AHDL_TDO_FILE = OFF;
END;

COMPILER_INTERFACES_CONFIGURATION
BEGIN
	EDIF_OUTPUT_VERSION = 300;
	EDIF_OUTPUT_EDC_FILE = "e:\berryhill\hitfinder\hitman\*.edc";
	EDIF_NETLIST_WRITER = ON;
	VHDL_FLATTEN_BUS = OFF;
	VERILOG_FLATTEN_BUS = OFF;
	NETLIST_OUTPUT_TIME_SCALE = 0.1ns;
	EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF;
	EDIF_BUS_DELIMITERS = ();
	EDIF_FLATTEN_BUS = OFF;
	EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF;
	EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = ON;
	EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
	EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE;
	EDIF_OUTPUT_USE_EDC = OFF;
	EDIF_INPUT_USE_LMF2 = OFF;
	EDIF_INPUT_USE_LMF1 = OFF;
	EDIF_OUTPUT_GND = GND;
	EDIF_OUTPUT_VCC = VCC;
	EDIF_INPUT_GND = GND;
	EDIF_INPUT_VCC = VCC;
	EDIF_INPUT_LMF2 = *.lmf;
	EDIF_INPUT_LMF1 = *.lmf;
	VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF;
	VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE;
	VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE;
	EDIF_TRUNCATE_HIERARCHY_PATH = OFF;
	VHDL_TRUNCATE_HIERARCHY_PATH = OFF;
	VERILOG_TRUNCATE_HIERARCHY_PATH = OFF;
	VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
	XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC;
	XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON;
	XNF_GENERATE_AHDL_TDX_FILE = ON;
	VERILOG_NETLIST_WRITER = OFF;
	VHDL_NETLIST_WRITER = OFF;
	USE_SYNOPSYS_SYNTHESIS = OFF;
	SYNOPSYS_COMPILER = DESIGN;
	SYNOPSYS_DESIGNWARE = OFF;
	SYNOPSYS_HIERARCHICAL_COMPILATION = ON;
	SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF;
	SYNOPSYS_MAPPING_EFFORT = MEDIUM;
	VHDL_READER_VERSION = VHDL87;
	VHDL_WRITER_VERSION = VHDL87;
END;

CUSTOM_DESIGN_DOCTOR_RULES
BEGIN
	RIPPLE_CLOCKS = ON;
	GATED_CLOCKS = ON;
	MULTI_LEVEL_CLOCKS = ON;
	MULTI_CLOCK_NETWORKS = ON;
	STATIC_HAZARDS_BEFORE_SYNTHESIS = ON;
	STATIC_HAZARDS_AFTER_SYNTHESIS = OFF;
	PRESET_CLEAR_NETWORKS = ON;
	ASYNCHRONOUS_INPUTS = ON;
	DELAY_CHAINS = ON;
	RACE_CONDITIONS = ON;
	EXPANDER_NETWORKS = ON;
	MASTER_RESET = OFF;
END;

SIMULATOR_CONFIGURATION
BEGIN
	BIDIR_PIN = STRONG;
	END_TIME = 7.5us;
	SETUP_HOLD = ON;
	USE_DEVICE = OFF;
	CHECK_OUTPUTS = OFF;
	OSCILLATION = OFF;
	OSCILLATION_TIME = 0.0ns;
	GLITCH = OFF;
	GLITCH_TIME = 0.0ns;
	START_TIME = 0.0ns;
END;

TIMING_ANALYZER_CONFIGURATION
BEGIN
	ANALYSIS_MODE = REGISTERED_PERFORMANCE;
	"|hmready:ready|svxdecode:svxdecoder|lpm_ff:validoutreg|dffs0.Q" :	DELAY_MATRIX_SOURCE;
	"|hmready:ready|lpm_ff:outdatareg|dffs17.Q" :	DELAY_MATRIX_SOURCE;
	"|hmready:ready|lpm_ff:outdatareg|dffs16.Q" :	DELAY_MATRIX_SOURCE;
	"|hmready:ready|lpm_ff:outdatareg|dffs15.Q" :	DELAY_MATRIX_SOURCE;
	"|hmready:ready|lpm_ff:outdatareg|dffs14.Q" :	DELAY_MATRIX_SOURCE;
	"|hmready:ready|lpm_ff:outdatareg|dffs13.Q" :	DELAY_MATRIX_SOURCE;
	"|hmready:ready|lpm_ff:outdatareg|dffs12.Q" :	DELAY_MATRIX_SOURCE;
	"|hmready:ready|lpm_ff:outdatareg|dffs11.Q" :	DELAY_MATRIX_SOURCE;
	"|hmready:ready|lpm_ff:outdatareg|dffs10.Q" :	DELAY_MATRIX_SOURCE;
	"|hmready:ready|lpm_ff:outdatareg|dffs9.Q" :	DELAY_MATRIX_SOURCE;
	"|hmready:ready|lpm_ff:outdatareg|dffs8.Q" :	DELAY_MATRIX_SOURCE;
	"|hmready:ready|lpm_ff:outdatareg|dffs7.Q" :	DELAY_MATRIX_SOURCE;
	"|hmready:ready|lpm_ff:outdatareg|dffs6.Q" :	DELAY_MATRIX_SOURCE;
	"|hmready:ready|lpm_ff:outdatareg|dffs5.Q" :	DELAY_MATRIX_SOURCE;
	"|hmready:ready|lpm_ff:outdatareg|dffs4.Q" :	DELAY_MATRIX_SOURCE;
	"|hmready:ready|lpm_ff:outdatareg|dffs3.Q" :	DELAY_MATRIX_SOURCE;
	"|hmready:ready|lpm_ff:outdatareg|dffs2.Q" :	DELAY_MATRIX_SOURCE;
	"|hmready:ready|lpm_ff:outdatareg|dffs1.Q" :	DELAY_MATRIX_SOURCE;
	"|hmready:ready|lpm_ff:outdatareg|dffs0.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_6~1~WE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_6~WE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_6~Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_6.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_6~D.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_6~BE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_6~A2.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_6~A1.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_6~A0.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_5~1~WE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_5~WE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_5~Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_5.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_5~D.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_5~BE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_5~A2.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_5~A1.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_5~A0.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_4~1~WE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_4~WE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_4~Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_4.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_4~D.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_4~BE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_4~A2.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_4~A1.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_4~A0.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_3~1~WE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_3~WE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_3~Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_3.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_3~D.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_3~BE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_3~A2.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_3~A1.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_3~A0.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_2~1~WE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_2~WE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_2~Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_2.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_2~D.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_2~BE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_2~A2.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_2~A1.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_2~A0.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_1~1~WE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_1~WE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_1~Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_1.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_1~D.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_1~BE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_1~A2.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_1~A1.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_1~A0.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_0~1~WE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_0~WE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_0~Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_0.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_0~D.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_0~BE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_0~A2.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_0~A1.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:thresholdram|altram:sram|segment0_0~A0.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_6~1~WE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_6~WE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_6~Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_6.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_6~D.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_6~BE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_6~A9.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_6~A8.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_6~A7.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_6~A6.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_6~A5.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_6~A4.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_6~A3.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_6~A2.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_6~A1.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_6~A0.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_5~1~WE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_5~WE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_5~Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_5.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_5~D.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_5~BE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_5~A9.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_5~A8.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_5~A7.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_5~A6.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_5~A5.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_5~A4.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_5~A3.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_5~A2.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_5~A1.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_5~A0.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_4~1~WE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_4~WE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_4~Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_4.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_4~D.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_4~BE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_4~A9.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_4~A8.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_4~A7.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_4~A6.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_4~A5.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_4~A4.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_4~A3.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_4~A2.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_4~A1.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_4~A0.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_3~1~WE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_3~WE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_3~Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_3.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_3~D.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_3~BE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_3~A9.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_3~A8.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_3~A7.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_3~A6.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_3~A5.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_3~A4.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_3~A3.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_3~A2.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_3~A1.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_3~A0.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_2~1~WE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_2~WE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_2~Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_2.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_2~D.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_2~BE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_2~A9.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_2~A8.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_2~A7.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_2~A6.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_2~A5.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_2~A4.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_2~A3.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_2~A2.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_2~A1.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_2~A0.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_1~1~WE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_1~WE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_1~Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_1.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_1~D.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_1~BE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_1~A9.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_1~A8.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_1~A7.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_1~A6.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_1~A5.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_1~A4.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_1~A3.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_1~A2.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_1~A1.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_1~A0.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_0~1~WE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_0~WE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_0~Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_0.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_0~D.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_0~BE.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_0~A9.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_0~A8.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_0~A7.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_0~A6.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_0~A5.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_0~A4.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_0~A3.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_0~A2.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_0~A1.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ram_dq:pedram|altram:sram|segment0_0~A0.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ff:dvalid|dffs0.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ff:dstrip|dffs9.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ff:dstrip|dffs8.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ff:dstrip|dffs7.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ff:dstrip|dffs6.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ff:dstrip|dffs5.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ff:dstrip|dffs4.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ff:dstrip|dffs3.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ff:dstrip|dffs2.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ff:dstrip|dffs1.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ff:dstrip|dffs0.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ff:dadc|dffs6.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ff:dadc|dffs5.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ff:dadc|dffs4.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ff:dadc|dffs3.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ff:dadc|dffs2.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ff:dadc|dffs1.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ff:dadc|dffs0.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ff:bvalid|dffs0.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ff:bvalid|dffs0.CLK" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ff:bstrip|dffs9.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ff:bstrip|dffs8.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ff:bstrip|dffs7.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ff:bstrip|dffs6.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ff:bstrip|dffs5.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ff:bstrip|dffs4.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ff:bstrip|dffs3.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ff:bstrip|dffs2.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ff:bstrip|dffs1.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ff:bstrip|dffs0.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ff:badc|dffs6.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ff:badc|dffs5.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ff:badc|dffs4.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ff:badc|dffs3.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ff:badc|dffs2.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ff:badc|dffs1.Q" :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ff:badc|dffs0.Q" :	DELAY_MATRIX_SOURCE;
	|hf_init_ff2.Q :	DELAY_MATRIX_SOURCE;
	"|hmaim:aim|lpm_ff:dvalid|dffs0.Q" :	DELAY_MATRIX_DESTINATION;
	CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF;
	"|hmfire:fire|engcen:148|cenpipe:93|LPM_FF:8|dffs0" :	REGISTERED_PERFORMANCE_SOURCE;
	AUTO_RECALCULATE = OFF;
	CUT_OFF_IO_PIN_FEEDBACK = ON;
	CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
	LIST_ONLY_LONGEST_PATH = ON;
	CELL_WIDTH = 18;
	DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS;
	INCLUDE_PATHS_GREATER_THAN = OFF;
	INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns;
	INCLUDE_PATHS_LESS_THAN = OFF;
	INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms;
	REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS;
	LIST_PATH_COUNT = 10;
	LIST_PATH_FREQUENCY = 10MHz;
END;

OTHER_CONFIGURATION
BEGIN
	LAST_MAXPLUS2_VERSION = 10.1;
	LCELLS_PER_ROW_PERCENT = 57;
	COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,1,1,1,1";
	ROW_PINS_LCELL_INSERT = ON;
	CARRY_OUT_PINS_LCELL_INSERT = OFF;
	NORMAL_LCELL_INSERT = ON;
	EXPLICIT_FAMILY = 1;
	ORIGINAL_MAXPLUS2_VERSION = 8.1;
	ROW_PINS_PERCENT = 50;
	EXP_PER_LCELL_PERCENT = 100;
	FAN_IN_PER_LCELL_PERCENT = 100;
	LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100;
	DEFAULT_9K_EXP_PER_LCELL = 1/2;
	FLEX_10K_52_COLUMNS = 40;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000
BEGIN
	CASCADE_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CARRY_CHAIN_LENGTH = -1;
	MINIMIZATION = FULL;
	SLOW_SLEW_RATE = OFF;
	XOR_SYNTHESIS = ON;
	TURBO_BIT = OFF;
	PARALLEL_EXPANDERS = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	FAST_IO = OFF;
	SOFT_BUFFER_INSERTION = ON;
	DECOMPOSE_GATES = ON;
	REDUCE_LOGIC = ON;
	DUPLICATE_LOGIC_EXTRACTION = ON;
	NOT_GATE_PUSH_BACK = ON;
	REFACTORIZATION = ON;
	SUBFACTOR_EXTRACTION = ON;
	MULTI_LEVEL_FACTORING = ON;
	RESYNTHESIZE_NETWORK = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	REGISTER_OPTIMIZATION = ON;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000
BEGIN
	CASCADE_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CARRY_CHAIN_LENGTH = -1;
	MINIMIZATION = FULL;
	SLOW_SLEW_RATE = OFF;
	XOR_SYNTHESIS = ON;
	TURBO_BIT = ON;
	PARALLEL_EXPANDERS = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	FAST_IO = OFF;
	SOFT_BUFFER_INSERTION = ON;
	DECOMPOSE_GATES = ON;
	REDUCE_LOGIC = ON;
	DUPLICATE_LOGIC_EXTRACTION = ON;
	NOT_GATE_PUSH_BACK = ON;
	REFACTORIZATION = ON;
	SUBFACTOR_EXTRACTION = ON;
	MULTI_LEVEL_FACTORING = ON;
	RESYNTHESIZE_NETWORK = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	REGISTER_OPTIMIZATION = ON;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC
BEGIN
	CASCADE_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CARRY_CHAIN_LENGTH = -1;
	MINIMIZATION = FULL;
	SLOW_SLEW_RATE = OFF;
	XOR_SYNTHESIS = OFF;
	TURBO_BIT = ON;
	PARALLEL_EXPANDERS = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	FAST_IO = OFF;
	SOFT_BUFFER_INSERTION = ON;
	DECOMPOSE_GATES = ON;
	REDUCE_LOGIC = OFF;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	REFACTORIZATION = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	MULTI_LEVEL_FACTORING = OFF;
	RESYNTHESIZE_NETWORK = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	REGISTER_OPTIMIZATION = OFF;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000
BEGIN
	CASCADE_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = 2;
	CARRY_CHAIN = IGNORE;
	CARRY_CHAIN_LENGTH = 32;
	MINIMIZATION = FULL;
	SLOW_SLEW_RATE = OFF;
	XOR_SYNTHESIS = OFF;
	TURBO_BIT = OFF;
	PARALLEL_EXPANDERS = OFF;
	IGNORE_SOFT_BUFFERS = ON;
	SOFT_BUFFER_INSERTION = ON;
	DECOMPOSE_GATES = ON;
	REDUCE_LOGIC = ON;
	DUPLICATE_LOGIC_EXTRACTION = ON;
	NOT_GATE_PUSH_BACK = ON;
	REFACTORIZATION = ON;
	SUBFACTOR_EXTRACTION = ON;
	MULTI_LEVEL_FACTORING = ON;
	RESYNTHESIZE_NETWORK = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	REGISTER_OPTIMIZATION = ON;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000
BEGIN
	CASCADE_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CARRY_CHAIN_LENGTH = -1;
	MINIMIZATION = FULL;
	SLOW_SLEW_RATE = OFF;
	XOR_SYNTHESIS = ON;
	TURBO_BIT = OFF;
	PARALLEL_EXPANDERS = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	FAST_IO = OFF;
	SOFT_BUFFER_INSERTION = ON;
	DECOMPOSE_GATES = ON;
	REDUCE_LOGIC = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	REFACTORIZATION = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	MULTI_LEVEL_FACTORING = ON;
	RESYNTHESIZE_NETWORK = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	REGISTER_OPTIMIZATION = ON;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000
BEGIN
	CASCADE_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CARRY_CHAIN_LENGTH = -1;
	MINIMIZATION = FULL;
	SLOW_SLEW_RATE = OFF;
	XOR_SYNTHESIS = ON;
	TURBO_BIT = ON;
	PARALLEL_EXPANDERS = ON;
	IGNORE_SOFT_BUFFERS = OFF;
	FAST_IO = OFF;
	SOFT_BUFFER_INSERTION = ON;
	DECOMPOSE_GATES = ON;
	REDUCE_LOGIC = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	REFACTORIZATION = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	MULTI_LEVEL_FACTORING = ON;
	RESYNTHESIZE_NETWORK = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	REGISTER_OPTIMIZATION = ON;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC
BEGIN
	CASCADE_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CARRY_CHAIN_LENGTH = -1;
	MINIMIZATION = FULL;
	SLOW_SLEW_RATE = OFF;
	XOR_SYNTHESIS = OFF;
	TURBO_BIT = ON;
	PARALLEL_EXPANDERS = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	FAST_IO = OFF;
	SOFT_BUFFER_INSERTION = ON;
	DECOMPOSE_GATES = ON;
	REDUCE_LOGIC = OFF;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	REFACTORIZATION = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	MULTI_LEVEL_FACTORING = OFF;
	RESYNTHESIZE_NETWORK = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	REGISTER_OPTIMIZATION = OFF;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000
BEGIN
	CASCADE_CHAIN = AUTO;
	CASCADE_CHAIN_LENGTH = 2;
	CARRY_CHAIN = AUTO;
	CARRY_CHAIN_LENGTH = 32;
	MINIMIZATION = FULL;
	SLOW_SLEW_RATE = OFF;
	XOR_SYNTHESIS = OFF;
	TURBO_BIT = OFF;
	PARALLEL_EXPANDERS = OFF;
	IGNORE_SOFT_BUFFERS = ON;
	SOFT_BUFFER_INSERTION = ON;
	DECOMPOSE_GATES = ON;
	REDUCE_LOGIC = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	REFACTORIZATION = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	MULTI_LEVEL_FACTORING = ON;
	RESYNTHESIZE_NETWORK = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	REGISTER_OPTIMIZATION = ON;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000
BEGIN
	CASCADE_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CARRY_CHAIN_LENGTH = -1;
	MINIMIZATION = PARTIAL;
	SLOW_SLEW_RATE = OFF;
	XOR_SYNTHESIS = OFF;
	TURBO_BIT = OFF;
	PARALLEL_EXPANDERS = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	FAST_IO = OFF;
	SOFT_BUFFER_INSERTION = OFF;
	DECOMPOSE_GATES = OFF;
	REDUCE_LOGIC = OFF;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	REFACTORIZATION = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	MULTI_LEVEL_FACTORING = OFF;
	RESYNTHESIZE_NETWORK = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	REGISTER_OPTIMIZATION = OFF;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000
BEGIN
	CASCADE_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CARRY_CHAIN_LENGTH = -1;
	MINIMIZATION = PARTIAL;
	SLOW_SLEW_RATE = OFF;
	XOR_SYNTHESIS = OFF;
	TURBO_BIT = ON;
	PARALLEL_EXPANDERS = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	FAST_IO = OFF;
	SOFT_BUFFER_INSERTION = OFF;
	DECOMPOSE_GATES = OFF;
	REDUCE_LOGIC = OFF;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	REFACTORIZATION = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	MULTI_LEVEL_FACTORING = OFF;
	RESYNTHESIZE_NETWORK = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	REGISTER_OPTIMIZATION = OFF;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC
BEGIN
	CASCADE_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CARRY_CHAIN_LENGTH = -1;
	MINIMIZATION = PARTIAL;
	SLOW_SLEW_RATE = OFF;
	XOR_SYNTHESIS = OFF;
	TURBO_BIT = ON;
	PARALLEL_EXPANDERS = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	FAST_IO = OFF;
	SOFT_BUFFER_INSERTION = OFF;
	DECOMPOSE_GATES = ON;
	REDUCE_LOGIC = OFF;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	REFACTORIZATION = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	MULTI_LEVEL_FACTORING = OFF;
	RESYNTHESIZE_NETWORK = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	REGISTER_OPTIMIZATION = OFF;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000
BEGIN
	CASCADE_CHAIN = MANUAL;
	CASCADE_CHAIN_LENGTH = 2;
	CARRY_CHAIN = MANUAL;
	CARRY_CHAIN_LENGTH = 32;
	MINIMIZATION = PARTIAL;
	SLOW_SLEW_RATE = OFF;
	XOR_SYNTHESIS = OFF;
	TURBO_BIT = OFF;
	PARALLEL_EXPANDERS = OFF;
	IGNORE_SOFT_BUFFERS = ON;
	SOFT_BUFFER_INSERTION = ON;
	DECOMPOSE_GATES = OFF;
	REDUCE_LOGIC = OFF;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	REFACTORIZATION = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	MULTI_LEVEL_FACTORING = OFF;
	RESYNTHESIZE_NETWORK = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	REGISTER_OPTIMIZATION = OFF;
END;