-- -- Copyright (C) 1988-2001 Altera Corporation -- Any megafunction design, and related net list (encrypted or decrypted), -- support information, device programming or simulation file, and any other -- associated documentation or information provided by Altera or a partner -- under Altera's Megafunction Partnership Program may be used only to -- program PLD devices (but not masked PLD devices) from Altera. Any other -- use of such megafunction design, net list, support information, device -- programming or simulation file, or any other related documentation or -- information is prohibited for any other purpose, including, but not -- limited to modification, reverse engineering, de-compiling, or use with -- any other silicon devices, unless such use is explicitly licensed under -- a separate agreement with Altera or a megafunction partner. Title to -- the intellectual property, including patents, copyrights, trademarks, -- trade secrets, or maskworks, embodied in any such megafunction design, -- net list, support information, device programming or simulation file, or -- any other related documentation or information provided by Altera or a -- megafunction partner, remains with Altera, the megafunction partner, or -- their respective licensors. No other licenses, including any licenses -- needed under any third party's intellectual property, are provided herein. -- CHIP merge BEGIN |vmedata17 : BIDIR_PIN = 33; |vmedata16 : BIDIR_PIN = 24; |vmedata15 : BIDIR_PIN = 26; |vmedata14 : BIDIR_PIN = 27; |vmedata13 : BIDIR_PIN = 25; |vmedata12 : BIDIR_PIN = 31; |vmedata11 : BIDIR_PIN = 35; |vmedata10 : BIDIR_PIN = 29; |vmedata9 : BIDIR_PIN = 40; |vmedata8 : BIDIR_PIN = 93; |vmedata7 : BIDIR_PIN = 36; |vmedata6 : BIDIR_PIN = 92; |vmedata5 : BIDIR_PIN = 96; |vmedata4 : BIDIR_PIN = 89; |vmedata3 : BIDIR_PIN = 15; |vmedata2 : BIDIR_PIN = 104; |vmedata1 : BIDIR_PIN = 2; |vmedata0 : BIDIR_PIN = 99; |afiforen4 : OUTPUT_PIN = 34; |afiforen3 : OUTPUT_PIN = 203; |afiforen2 : OUTPUT_PIN = 206; |afiforen1 : OUTPUT_PIN = 205; |afiforen0 : OUTPUT_PIN = 28; |bfiforen4 : OUTPUT_PIN = 8; |bfiforen3 : OUTPUT_PIN = 10; |bfiforen2 : OUTPUT_PIN = 4; |bfiforen1 : OUTPUT_PIN = 3; |bfiforen0 : OUTPUT_PIN = 21; |afifoclock4 : OUTPUT_PIN = 13; |afifoclock3 : OUTPUT_PIN = 16; |afifoclock2 : OUTPUT_PIN = 6; |afifoclock1 : OUTPUT_PIN = 9; |afifoclock0 : OUTPUT_PIN = 7; |bfifoclock4 : OUTPUT_PIN = 20; |bfifoclock3 : OUTPUT_PIN = 17; |bfifoclock2 : OUTPUT_PIN = 18; |bfifoclock1 : OUTPUT_PIN = 12; |bfifoclock0 : OUTPUT_PIN = 11; |hit17 : OUTPUT_PIN = 77; |hit16 : OUTPUT_PIN = 73; |hit15 : OUTPUT_PIN = 71; |hit14 : OUTPUT_PIN = 68; |hit13 : OUTPUT_PIN = 67; |hit12 : OUTPUT_PIN = 65; |hit11 : OUTPUT_PIN = 64; |hit10 : OUTPUT_PIN = 59; |hit9 : OUTPUT_PIN = 58; |hit8 : OUTPUT_PIN = 57; |hit6 : OUTPUT_PIN = 55; |hit5 : OUTPUT_PIN = 53; |hit4 : OUTPUT_PIN = 49; |hit3 : OUTPUT_PIN = 52; |hit2 : OUTPUT_PIN = 43; |hit1 : OUTPUT_PIN = 44; |hit0 : OUTPUT_PIN = 45; |stream5 : OUTPUT_PIN = 47; |stream4 : OUTPUT_PIN = 199; |stream3 : OUTPUT_PIN = 198; |stream2 : OUTPUT_PIN = 48; |stream1 : OUTPUT_PIN = 78; |stream0 : OUTPUT_PIN = 190; |outclock : OUTPUT_PIN = 197; |Merger_Spare : OUTPUT_PIN = 188; |vmespare : INPUT_PIN = 113; |HF_Spare : INPUT_PIN = 76; |clock : INPUT_PIN = 184; |hf_init : INPUT_PIN = 160; |hold : INPUT_PIN = 147; |vmeaddress5 : INPUT_PIN = 156; |vmeaddress4 : INPUT_PIN = 149; |vmeaddress2 : INPUT_PIN = 130; |vmeaddress3 : INPUT_PIN = 145; |vmeaddress10 : INPUT_PIN = 171; |vmeaddress9 : INPUT_PIN = 167; |vmeaddress8 : INPUT_PIN = 162; |vmeaddress6 : INPUT_PIN = 155; |vmeaddress7 : INPUT_PIN = 153; |vme_as : INPUT_PIN = 131; |hf_load : INPUT_PIN = 129; |vmeclock : INPUT_PIN = 181; |hf_test : INPUT_PIN = 136; |bfifohit17 : INPUT_PIN = 103; |afifohit17 : INPUT_PIN = 126; |bfifohit16 : INPUT_PIN = 84; |afifohit16 : INPUT_PIN = 117; |bfifohit14 : INPUT_PIN = 159; |afifohit14 : INPUT_PIN = 139; |bfifohit13 : INPUT_PIN = 157; |afifohit13 : INPUT_PIN = 172; |bfifohit12 : INPUT_PIN = 164; |afifohit12 : INPUT_PIN = 151; |bfifohit11 : INPUT_PIN = 173; |afifohit11 : INPUT_PIN = 178; |bfifohit10 : INPUT_PIN = 81; |afifohit10 : INPUT_PIN = 133; |vmeaddress0 : INPUT_PIN = 123; |bfifohit15 : INPUT_PIN = 177; |afifohit15 : INPUT_PIN = 170; |bfifohit9 : INPUT_PIN = 101; |bfifoef4 : INPUT_PIN = 122; |vmeaddress1 : INPUT_PIN = 175; |afifohit9 : INPUT_PIN = 100; |bfifohit8 : INPUT_PIN = 120; |bfifoef3 : INPUT_PIN = 118; |afifohit8 : INPUT_PIN = 121; |bfifohit7 : INPUT_PIN = 132; |bfifoef2 : INPUT_PIN = 161; |afifohit7 : INPUT_PIN = 79; |bfifohit6 : INPUT_PIN = 106; |bfifoef1 : INPUT_PIN = 166; |afifohit6 : INPUT_PIN = 115; |bfifohit5 : INPUT_PIN = 91; |bfifoef0 : INPUT_PIN = 168; |afifohit5 : INPUT_PIN = 128; |bfifohit4 : INPUT_PIN = 119; |afifoef4 : INPUT_PIN = 150; |afifohit4 : INPUT_PIN = 140; |bfifohit3 : INPUT_PIN = 110; |afifoef3 : INPUT_PIN = 163; |afifohit3 : INPUT_PIN = 95; |bfifohit2 : INPUT_PIN = 138; |afifoef2 : INPUT_PIN = 154; |afifohit2 : INPUT_PIN = 137; |bfifohit1 : INPUT_PIN = 114; |afifoef1 : INPUT_PIN = 148; |afifohit1 : INPUT_PIN = 80; |bfifohit0 : INPUT_PIN = 112; |afifohit0 : INPUT_PIN = 142; |afifoef0 : INPUT_PIN = 146; |hit7 : OUTPUT_PIN = 61; |vmewrite : INPUT_PIN = 169; DEVICE = EPM7512AEQC208-7; END; DEFAULT_DEVICES BEGIN AUTO_DEVICE = EPM7512AEFC256-7; AUTO_DEVICE = EPM7512AEQC208-7; AUTO_DEVICE = EPM7512AETC144-7; AUTO_DEVICE = EPM7064AEFC100-5; AUTO_DEVICE = EPM7064AETC100-5; AUTO_DEVICE = EPM7064AELC84-5; AUTO_DEVICE = EPM7064AETC44-5; AUTO_DEVICE = EPM7064AELC44-5; ASK_BEFORE_ADDING_EXTRA_DEVICES = ON; END; TIMING_POINT BEGIN DEVICE_FOR_TIMING_SYNTHESIS = EPM7512AEQC208-7; |clock : FREQUENCY = 40MHz; MAINTAIN_STABLE_SYNTHESIS = OFF; CUT_ALL_BIDIR = ON; CUT_ALL_CLEAR_PRESET = ON; END; CLIQUE afifologic BEGIN "|fifologic:afifologic" : CLIQUE; END; CLIQUE bfifologic BEGIN "|fifologic:bfifologic" : CLIQUE; END; IGNORED_ASSIGNMENTS BEGIN IGNORE_PIN_ASSIGNMENTS = OFF; FIT_IGNORE_TIMING = OFF; IGNORE_CLIQUE_ASSIGNMENTS = OFF; IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF; IGNORE_TIMING_ASSIGNMENTS = OFF; IGNORE_CHIP_ASSIGNMENTS = OFF; IGNORE_LC_ASSIGNMENTS = OFF; IGNORE_DEVICE_ASSIGNMENTS = OFF; IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF; DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF; END; LOGIC_OPTIONS BEGIN |vmedata17 : SLOW_SLEW_RATE = ON; |vmedata16 : SLOW_SLEW_RATE = ON; |vmedata15 : SLOW_SLEW_RATE = ON; |vmedata14 : SLOW_SLEW_RATE = ON; |vmedata13 : SLOW_SLEW_RATE = ON; |vmedata12 : SLOW_SLEW_RATE = ON; |vmedata11 : SLOW_SLEW_RATE = ON; |vmedata10 : SLOW_SLEW_RATE = ON; |vmedata9 : SLOW_SLEW_RATE = ON; |vmedata8 : SLOW_SLEW_RATE = ON; |vmedata7 : SLOW_SLEW_RATE = ON; |vmedata6 : SLOW_SLEW_RATE = ON; |vmedata5 : SLOW_SLEW_RATE = ON; |vmedata4 : SLOW_SLEW_RATE = ON; |vmedata3 : SLOW_SLEW_RATE = ON; |vmedata2 : SLOW_SLEW_RATE = ON; |vmedata1 : SLOW_SLEW_RATE = ON; |vmedata0 : SLOW_SLEW_RATE = ON; END; GLOBAL_PROJECT_DEVICE_OPTIONS BEGIN MAX7000B_ENABLE_VREFB = OFF; MAX7000B_ENABLE_VREFA = OFF; MAX7000B_VCCIO_IOBANK2 = 3.3V; MAX7000B_VCCIO_IOBANK1 = 3.3V; CONFIG_EPROM_PULLUP_RESISTOR = ON; CONFIG_EPROM_USER_CODE = FFFFFFFF; MAX7000AE_ENABLE_JTAG = ON; FLEX_CONFIGURATION_EPROM = AUTO; MAX7000AE_USER_CODE = FFFFFFFF; RESERVED_LCELLS_PERCENT = 0; RESERVED_PINS_PERCENT = 0; SECURITY_BIT = OFF; USER_CLOCK = OFF; AUTO_RESTART = OFF; RELEASE_CLEARS = OFF; ENABLE_DCLK_OUTPUT = OFF; DISABLE_TIME_OUT = OFF; CONFIG_SCHEME = ACTIVE_SERIAL; FLEX8000_ENABLE_JTAG = OFF; DATA0 = RESERVED_TRI_STATED; DATA1_TO_DATA7 = UNRESERVED; nWS_nRS_nCS_CS = UNRESERVED; RDYnBUSY = UNRESERVED; RDCLK = UNRESERVED; SDOUT = RESERVED_DRIVES_OUT; ADD0_TO_ADD12 = UNRESERVED; ADD13 = UNRESERVED; ADD14 = UNRESERVED; ADD15 = UNRESERVED; ADD16 = UNRESERVED; ADD17 = UNRESERVED; CLKUSR = UNRESERVED; nCEO = UNRESERVED; ENABLE_CHIP_WIDE_RESET = OFF; ENABLE_CHIP_WIDE_OE = OFF; ENABLE_INIT_DONE_OUTPUT = OFF; FLEX10K_JTAG_USER_CODE = 7F; CONFIG_SCHEME_10K = PASSIVE_SERIAL; MAX7000S_USER_CODE = FFFF; FLEX10K_ENABLE_LOCK_OUTPUT = OFF; MAX7000S_ENABLE_JTAG = ON; MULTIVOLT_IO = OFF; CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL; FLEX6000_ENABLE_JTAG = OFF; FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF; FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON; FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF; END; GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS BEGIN AUTO_FAST_IO = OFF; ONE_HOT_STATE_MACHINE_ENCODING = ON; AUTO_GLOBAL_CLEAR = OFF; AUTO_IMPLEMENT_IN_EAB = ON; MULTI_LEVEL_SYNTHESIS_MAX9000 = OFF; MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = ON; DEVICE_FAMILY = MAX7000AE; AUTO_GLOBAL_CLOCK = ON; AUTO_OPEN_DRAIN_PINS = ON; STYLE = FAST; AUTO_REGISTER_PACKING = ON; OPTIMIZE_FOR_SPEED = 10; AUTO_GLOBAL_PRESET = OFF; AUTO_GLOBAL_OE = OFF; END; COMPILER_PROCESSING_CONFIGURATION BEGIN DESIGN_DOCTOR = OFF; OPTIMIZE_TIMING_SNF = ON; SMART_RECOMPILE = ON; DESIGN_DOCTOR_RULES = EPLD; FUNCTIONAL_SNF_EXTRACTOR = OFF; TIMING_SNF_EXTRACTOR = ON; LINKED_SNF_EXTRACTOR = OFF; RPT_FILE_EQUATIONS = ON; RPT_FILE_HIERARCHY = ON; RPT_FILE_LCELL_INTERCONNECT = ON; RPT_FILE_USER_ASSIGNMENTS = ON; GENERATE_AHDL_TDO_FILE = OFF; FITTER_SETTINGS = NORMAL; PRESERVE_ALL_NODE_NAME_SYNONYMS = ON; END; COMPILER_INTERFACES_CONFIGURATION BEGIN EDIF_OUTPUT_VERSION = 300; EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF; EDIF_OUTPUT_GND = GND; EDIF_NETLIST_WRITER = ON; EDIF_BUS_DELIMITERS = (); EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = ON; EDIF_OUTPUT_EDC_FILE = "e:\berryhill\hitfinder\merger\*.edc"; VHDL_FLATTEN_BUS = OFF; VERILOG_FLATTEN_BUS = OFF; NETLIST_OUTPUT_TIME_SCALE = 0.1ns; EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF; EDIF_FLATTEN_BUS = OFF; EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF; EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE; EDIF_OUTPUT_USE_EDC = OFF; EDIF_INPUT_USE_LMF2 = OFF; EDIF_INPUT_USE_LMF1 = OFF; EDIF_OUTPUT_VCC = VCC; EDIF_INPUT_GND = GND; EDIF_INPUT_VCC = VCC; EDIF_INPUT_LMF2 = *.lmf; EDIF_INPUT_LMF1 = *.lmf; VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF; VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE; VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE; EDIF_TRUNCATE_HIERARCHY_PATH = OFF; VHDL_TRUNCATE_HIERARCHY_PATH = OFF; VERILOG_TRUNCATE_HIERARCHY_PATH = OFF; VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF; XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC; XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON; XNF_GENERATE_AHDL_TDX_FILE = ON; VERILOG_NETLIST_WRITER = OFF; VHDL_NETLIST_WRITER = OFF; USE_SYNOPSYS_SYNTHESIS = OFF; SYNOPSYS_COMPILER = DESIGN; SYNOPSYS_DESIGNWARE = OFF; SYNOPSYS_HIERARCHICAL_COMPILATION = ON; SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF; SYNOPSYS_MAPPING_EFFORT = MEDIUM; VHDL_READER_VERSION = VHDL87; VHDL_WRITER_VERSION = VHDL87; END; CUSTOM_DESIGN_DOCTOR_RULES BEGIN RIPPLE_CLOCKS = ON; GATED_CLOCKS = ON; MULTI_LEVEL_CLOCKS = ON; MULTI_CLOCK_NETWORKS = ON; STATIC_HAZARDS_BEFORE_SYNTHESIS = ON; STATIC_HAZARDS_AFTER_SYNTHESIS = OFF; PRESET_CLEAR_NETWORKS = ON; ASYNCHRONOUS_INPUTS = ON; DELAY_CHAINS = ON; RACE_CONDITIONS = ON; EXPANDER_NETWORKS = ON; MASTER_RESET = OFF; END; SIMULATOR_CONFIGURATION BEGIN BIDIR_PIN = STRONG; SETUP_HOLD = ON; USE_DEVICE = OFF; CHECK_OUTPUTS = OFF; OSCILLATION = OFF; OSCILLATION_TIME = 0.0ns; GLITCH = OFF; GLITCH_TIME = 0.0ns; START_TIME = 0.0ns; END_TIME = 1.0us; END; TIMING_ANALYZER_CONFIGURATION BEGIN CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF; AUTO_RECALCULATE = OFF; CUT_OFF_IO_PIN_FEEDBACK = ON; CUT_OFF_CLEAR_AND_PRESET_PATHS = ON; LIST_ONLY_LONGEST_PATH = ON; CELL_WIDTH = 18; DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS; INCLUDE_PATHS_GREATER_THAN = OFF; INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns; INCLUDE_PATHS_LESS_THAN = OFF; INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms; REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS; LIST_PATH_COUNT = 10; LIST_PATH_FREQUENCY = 10MHz; ANALYSIS_MODE = REGISTERED_PERFORMANCE; END; OTHER_CONFIGURATION BEGIN LAST_MAXPLUS2_VERSION = 10.1; COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,1,1,1,1"; EXPLICIT_FAMILY = 1; ORIGINAL_MAXPLUS2_VERSION = 8.1; ROW_PINS_PERCENT = 50; EXP_PER_LCELL_PERCENT = 100; FAN_IN_PER_LCELL_PERCENT = 100; LCELLS_PER_ROW_PERCENT = 100; LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100; DEFAULT_9K_EXP_PER_LCELL = 1/2; FLEX_10K_52_COLUMNS = 40; END; DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = ON; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = OFF; FAST_IO = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = ON; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = ON; SUBFACTOR_EXTRACTION = ON; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = ON; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = OFF; FAST_IO = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = ON; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = ON; SUBFACTOR_EXTRACTION = ON; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = OFF; FAST_IO = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = 2; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = 32; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = ON; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = ON; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = ON; SUBFACTOR_EXTRACTION = ON; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = ON; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = OFF; FAST_IO = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = ON; TURBO_BIT = ON; PARALLEL_EXPANDERS = ON; IGNORE_SOFT_BUFFERS = OFF; FAST_IO = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = OFF; FAST_IO = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000 BEGIN CASCADE_CHAIN = AUTO; CASCADE_CHAIN_LENGTH = 2; CARRY_CHAIN = AUTO; CARRY_CHAIN_LENGTH = 32; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = ON; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; MINIMIZATION = PARTIAL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = OFF; FAST_IO = OFF; SOFT_BUFFER_INSERTION = OFF; DECOMPOSE_GATES = OFF; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = OFF; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; MINIMIZATION = PARTIAL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = OFF; FAST_IO = OFF; SOFT_BUFFER_INSERTION = OFF; DECOMPOSE_GATES = OFF; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = OFF; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; MINIMIZATION = PARTIAL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = OFF; FAST_IO = OFF; SOFT_BUFFER_INSERTION = OFF; DECOMPOSE_GATES = ON; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000 BEGIN CASCADE_CHAIN = MANUAL; CASCADE_CHAIN_LENGTH = 2; CARRY_CHAIN = MANUAL; CARRY_CHAIN_LENGTH = 32; MINIMIZATION = PARTIAL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = ON; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = OFF; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = OFF; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = OFF; END;