-- -- Copyright (C) 1988-1998 Altera Corporation -- Any megafunction design, and related net list (encrypted or decrypted), -- support information, device programming or simulation file, and any other -- associated documentation or information provided by Altera or a partner -- under Altera's Megafunction Partnership Program may be used only to -- program PLD devices (but not masked PLD devices) from Altera. Any other -- use of such megafunction design, net list, support information, device -- programming or simulation file, or any other related documentation or -- information is prohibited for any other purpose, including, but not -- limited to modification, reverse engineering, de-compiling, or use with -- any other silicon devices, unless such use is explicitly licensed under -- a separate agreement with Altera or a megafunction partner. Title to -- the intellectual property, including patents, copyrights, trademarks, -- trade secrets, or maskworks, embodied in any such megafunction design, -- net list, support information, device programming or simulation file, or -- any other related documentation or information provided by Altera or a -- megafunction partner, remains with Altera, the megafunction partner, or -- their respective licensors. No other licenses, including any licenses -- needed under any third party's intellectual property, are provided herein. -- CHIP fep BEGIN |LV_power : OUTPUT_PIN = B7; |road2 : OUTPUT_PIN = AM17; |N_init_fit : OUTPUT_PIN = E28; |N_init_led : OUTPUT_PIN = B17; |run_mode : INPUT_PIN = AL19; |spy_clk_in : INPUT_PIN = E26; |t2clk : INPUT_PIN = E27; |road0 : OUTPUT_PIN = AR16; |road1 : OUTPUT_PIN = AR17; |road3 : OUTPUT_PIN = AR20; |road4 : OUTPUT_PIN = AR21; |road5 : OUTPUT_PIN = AR22; |road6 : OUTPUT_PIN = AR24; |road7 : OUTPUT_PIN = AP16; |road8 : OUTPUT_PIN = AP17; |road9 : OUTPUT_PIN = AP18; |road10 : OUTPUT_PIN = AP19; |road11 : OUTPUT_PIN = AP20; |road12 : OUTPUT_PIN = AP21; |road13 : OUTPUT_PIN = AP22; |road14 : OUTPUT_PIN = AP23; |zid0 : OUTPUT_PIN = AN20; |zid1 : OUTPUT_PIN = AN21; |zid2 : OUTPUT_PIN = AN22; |zid3 : OUTPUT_PIN = AN23; |zid4 : OUTPUT_PIN = AN24; |zid5 : OUTPUT_PIN = AN25; |fep_state0 : OUTPUT_PIN = AL22; |fep_state1 : OUTPUT_PIN = AL21; |fep_state2 : OUTPUT_PIN = AL20; |parity_err : OUTPUT_PIN = AN19; |tst_mode0 : INPUT_PIN = AN18; |tst_mode1 : INPUT_PIN = AN17; |N_freeze : INPUT_PIN = AM18; |hold_fep : INPUT_PIN = A16; |src_config : INPUT_PIN = A6; |N_fifo_empty2 : INPUT_PIN = AR10; |N_fifo_empty3 : INPUT_PIN = AR12; |N_fifo_empty4 : INPUT_PIN = AR13; |N_fifo_empty5 : INPUT_PIN = AR14; |N_fifo_empty6 : INPUT_PIN = AR15; |N_fifo_empty7 : INPUT_PIN = AP10; |N_fifo_afull2 : INPUT_PIN = AP11; |N_fifo_afull3 : INPUT_PIN = AP12; |N_fifo_afull4 : INPUT_PIN = AP13; |N_fifo_afull5 : INPUT_PIN = AP14; |N_fifo_afull6 : INPUT_PIN = AP15; |N_fifo_afull7 : INPUT_PIN = AN10; |N_fifo_full2 : INPUT_PIN = AN11; |N_fifo_full3 : INPUT_PIN = AN12; |N_fifo_full4 : INPUT_PIN = AN13; |N_fifo_full5 : INPUT_PIN = AN14; |N_fifo_full6 : INPUT_PIN = AN16; |N_fifo_full7 : INPUT_PIN = AM16; |N_modsel : INPUT_PIN = H2; |vme_wrt : INPUT_PIN = H3; |vme_tap0 : INPUT_PIN = H4; |vme_tap1 : INPUT_PIN = J1; |vme_tap2 : INPUT_PIN = J2; |vme_tap3 : INPUT_PIN = J3; |vme_tap4 : INPUT_PIN = J4; |vme_addr0 : INPUT_PIN = J5; |vme_addr1 : INPUT_PIN = K1; |vme_addr2 : INPUT_PIN = K2; |vme_addr3 : INPUT_PIN = K3; |vme_addr4 : INPUT_PIN = K4; |vme_addr5 : INPUT_PIN = K5; |vme_addr6 : INPUT_PIN = L1; |vme_addr7 : INPUT_PIN = L2; |vme_addr8 : INPUT_PIN = L3; |vme_addr9 : INPUT_PIN = L4; |vme_addr10 : INPUT_PIN = L5; |vme_addr11 : INPUT_PIN = M1; |vme_addr12 : INPUT_PIN = M3; |vme_addr13 : INPUT_PIN = M4; |vme_addr14 : INPUT_PIN = M5; |vme_addr15 : INPUT_PIN = N1; |vme_addr16 : INPUT_PIN = N2; |vme_addr17 : INPUT_PIN = N3; |vme_addr18 : INPUT_PIN = N4; |vme_addr19 : INPUT_PIN = N5; |vme_addr20 : INPUT_PIN = P1; |vme_addr21 : INPUT_PIN = P2; |vme_addr22 : INPUT_PIN = P3; |vme_addr23 : INPUT_PIN = P4; |vme_addr24 : INPUT_PIN = R1; |vme_data0 : BIDIR_PIN = T1; |vme_data1 : BIDIR_PIN = T2; |vme_data2 : BIDIR_PIN = T3; |vme_data3 : BIDIR_PIN = T4; |vme_data4 : BIDIR_PIN = T5; |vme_data5 : BIDIR_PIN = U1; |vme_data6 : BIDIR_PIN = U2; |vme_data7 : BIDIR_PIN = U4; |vme_data8 : BIDIR_PIN = U5; |vme_data9 : BIDIR_PIN = V1; |vme_data10 : BIDIR_PIN = V2; |vme_data11 : BIDIR_PIN = V3; |vme_data12 : BIDIR_PIN = V4; |vme_data13 : BIDIR_PIN = V5; |vme_data14 : BIDIR_PIN = W1; |vme_data15 : BIDIR_PIN = W2; |vme_data16 : BIDIR_PIN = W3; |vme_data17 : BIDIR_PIN = W4; |vme_data18 : BIDIR_PIN = W5; |vme_data19 : BIDIR_PIN = Y1; |vme_data20 : BIDIR_PIN = Y3; |vme_data21 : BIDIR_PIN = Y4; |vme_data22 : BIDIR_PIN = Y5; |vme_data23 : BIDIR_PIN = AA1; |vme_data24 : BIDIR_PIN = AA2; |vme_data25 : BIDIR_PIN = AA3; |vme_data26 : BIDIR_PIN = AA4; |vme_data27 : BIDIR_PIN = AA5; |vme_data28 : BIDIR_PIN = AB1; |vme_data29 : BIDIR_PIN = AB2; |vme_data30 : BIDIR_PIN = AB3; |vme_data31 : BIDIR_PIN = AB4; |N_tf_clk : INPUT_PIN = AL18; |N_init : INPUT_PIN = C18; |tf_clk : INPUT_PIN = E18; |hit_spare0 : OUTPUT_PIN = N35; |hit_spare1 : OUTPUT_PIN = M31; |hit_spare2 : OUTPUT_PIN = M32; |hit_spare3 : OUTPUT_PIN = M33; |hit_spare4 : OUTPUT_PIN = M34; |hit_spare5 : OUTPUT_PIN = M35; |hit_spare6 : OUTPUT_PIN = L31; |hit_spare7 : OUTPUT_PIN = L32; |hitlyr0 : OUTPUT_PIN = L33; |hitlyr1 : OUTPUT_PIN = L34; |hitlyr2 : OUTPUT_PIN = K31; |hitlyr3 : OUTPUT_PIN = K33; |hitlyr4 : OUTPUT_PIN = K34; |hitlyr5 : OUTPUT_PIN = K35; |oflow_lyr : OUTPUT_PIN = J31; |oflow_cmb : OUTPUT_PIN = J32; |oflow_hit : OUTPUT_PIN = J33; |outorder : OUTPUT_PIN = J34; |uflow_hit : OUTPUT_PIN = J35; |sector0 : OUTPUT_PIN = H35; |sector1 : OUTPUT_PIN = H34; |sector2 : OUTPUT_PIN = H33; |sector3 : OUTPUT_PIN = H32; |N_tffifo_reset : OUTPUT_PIN = L35; |N_tffifo_wena : OUTPUT_PIN = AR29; |fep_dout0 : OUTPUT_PIN = AM35; |fep_dout1 : OUTPUT_PIN = AM34; |fep_dout2 : OUTPUT_PIN = AM33; |fep_dout3 : OUTPUT_PIN = AM29; |fep_dout4 : OUTPUT_PIN = AM28; |fep_dout5 : OUTPUT_PIN = AM27; |fep_dout6 : OUTPUT_PIN = AM25; |fep_dout7 : OUTPUT_PIN = AM24; |fep_dout8 : OUTPUT_PIN = AM23; |fep_dout9 : OUTPUT_PIN = AM22; |fep_dout10 : OUTPUT_PIN = AM21; |fep_dout11 : OUTPUT_PIN = AM20; |fep_dout12 : OUTPUT_PIN = AL35; |fep_dout13 : OUTPUT_PIN = AL34; |fep_dout14 : OUTPUT_PIN = AL33; |fep_dout15 : OUTPUT_PIN = AL32; |fep_dout16 : OUTPUT_PIN = AL29; |fep_dout17 : OUTPUT_PIN = AL28; |fep_dout18 : OUTPUT_PIN = AL27; |fep_dout19 : OUTPUT_PIN = AL26; |fep_dout20 : OUTPUT_PIN = AL25; |fep_dout21 : OUTPUT_PIN = AL24; |fep_dout22 : OUTPUT_PIN = AL23; |hitout60 : OUTPUT_PIN = P35; |hitout61 : OUTPUT_PIN = N31; |hitout62 : OUTPUT_PIN = N32; |hitout63 : OUTPUT_PIN = N33; |hitout0 : OUTPUT_PIN = AK32; |hitout1 : OUTPUT_PIN = AK33; |hitout2 : OUTPUT_PIN = AK34; |hitout3 : OUTPUT_PIN = AJ31; |hitout4 : OUTPUT_PIN = AJ32; |hitout5 : OUTPUT_PIN = AJ33; |hitout6 : OUTPUT_PIN = AJ34; |hitout7 : OUTPUT_PIN = AH31; |hitout8 : OUTPUT_PIN = AH32; |hitout9 : OUTPUT_PIN = AH33; |hitout10 : OUTPUT_PIN = AH34; |hitout11 : OUTPUT_PIN = AH35; |hitout12 : OUTPUT_PIN = AG31; |hitout13 : OUTPUT_PIN = AG32; |hitout14 : OUTPUT_PIN = AG33; |hitout15 : OUTPUT_PIN = AG34; |hitout16 : OUTPUT_PIN = AG35; |hitout17 : OUTPUT_PIN = AF31; |hitout18 : OUTPUT_PIN = AF33; |hitout19 : OUTPUT_PIN = AF34; |hitout20 : OUTPUT_PIN = AF35; |hitout21 : OUTPUT_PIN = AE31; |hitout22 : OUTPUT_PIN = AE32; |hitout23 : OUTPUT_PIN = AB35; |hitout24 : OUTPUT_PIN = AA31; |hitout25 : OUTPUT_PIN = AA32; |hitout26 : OUTPUT_PIN = AA34; |hitout27 : OUTPUT_PIN = AA35; |hitout28 : OUTPUT_PIN = Y31; |hitout29 : OUTPUT_PIN = Y32; |hitout30 : OUTPUT_PIN = Y33; |hitout31 : OUTPUT_PIN = Y34; |hitout32 : OUTPUT_PIN = Y35; |hitout33 : OUTPUT_PIN = W31; |hitout34 : OUTPUT_PIN = W32; |hitout35 : OUTPUT_PIN = W33; |hitout36 : OUTPUT_PIN = W34; |hitout37 : OUTPUT_PIN = W35; |hitout38 : OUTPUT_PIN = V31; |hitout39 : OUTPUT_PIN = V33; |hitout40 : OUTPUT_PIN = V34; |hitout41 : OUTPUT_PIN = V35; |hitout42 : OUTPUT_PIN = U31; |hitout43 : OUTPUT_PIN = U32; |hitout44 : OUTPUT_PIN = U33; |hitout45 : OUTPUT_PIN = U34; |hitout46 : OUTPUT_PIN = U35; |hitout47 : OUTPUT_PIN = T31; |hitout48 : OUTPUT_PIN = T32; |hitout49 : OUTPUT_PIN = T33; |hitout50 : OUTPUT_PIN = T34; |hitout51 : OUTPUT_PIN = R31; |hitout52 : OUTPUT_PIN = R32; |hitout53 : OUTPUT_PIN = R33; |hitout54 : OUTPUT_PIN = R34; |hitout55 : OUTPUT_PIN = R35; |hitout56 : OUTPUT_PIN = P31; |hitout57 : OUTPUT_PIN = P32; |hitout58 : OUTPUT_PIN = P33; |hitout59 : OUTPUT_PIN = P34; |spy_data0 : BIDIR_PIN = A21; |spy_data1 : BIDIR_PIN = A22; |spy_data2 : BIDIR_PIN = A23; |spy_data3 : BIDIR_PIN = A24; |spy_data4 : BIDIR_PIN = B19; |spy_data5 : BIDIR_PIN = B20; |spy_data6 : BIDIR_PIN = B21; |spy_data7 : BIDIR_PIN = B22; |spy_data8 : BIDIR_PIN = B23; |spy_data9 : BIDIR_PIN = B24; |spy_data10 : BIDIR_PIN = C19; |spy_data11 : BIDIR_PIN = C20; |spy_data12 : BIDIR_PIN = C21; |spy_data13 : BIDIR_PIN = C22; |spy_data14 : BIDIR_PIN = C24; |spy_data15 : BIDIR_PIN = D19; |spy_data16 : BIDIR_PIN = D20; |spy_data17 : BIDIR_PIN = D21; |spy_data18 : BIDIR_PIN = D22; |spy_data19 : BIDIR_PIN = D23; |spy_data20 : BIDIR_PIN = E19; |spy_data21 : BIDIR_PIN = E20; |spy_data22 : BIDIR_PIN = E21; |spy_data23 : BIDIR_PIN = E22; |spy_data24 : BIDIR_PIN = E23; |spy_data25 : BIDIR_PIN = E24; |tffifo_empty : OUTPUT_PIN = AN28; |tffifo_full : OUTPUT_PIN = AN27; |hbfifo_full : OUTPUT_PIN = AN26; |fitc_spare : INPUT_PIN = AP29; |opp_spare : INPUT_PIN = AN29; |fep_spare : OUTPUT_PIN = AR28; |tmod_run : INPUT_PIN = AP28; |svt_din22 : INPUT_PIN = E10; |N_hbfifo_rena : OUTPUT_PIN = E11; |N_fifo_empty0 : INPUT_PIN = E13; |N_fifo_empty1 : INPUT_PIN = E14; |N_fifo_full0 : INPUT_PIN = E15; |N_fifo_full1 : INPUT_PIN = E16; |N_fifo_afull0 : INPUT_PIN = D16; |N_fifo_afull1 : INPUT_PIN = C16; |opp_busy : INPUT_PIN = AP25; |opp_done : INPUT_PIN = AP26; |fitter_busy : INPUT_PIN = AP27; |fepin_busy : OUTPUT_PIN = AR25; |fepout_busy : OUTPUT_PIN = AR26; |fep_eoe : OUTPUT_PIN = AR27; |spy_cnt_ena : INPUT_PIN = D27; |spy_ena_out : OUTPUT_PIN = D28; |N_spy_wena : OUTPUT_PIN = D29; |N_spy_oena : OUTPUT_PIN = E25; |spy_addr0 : OUTPUT_PIN = A25; |spy_addr1 : OUTPUT_PIN = A26; |spy_addr2 : OUTPUT_PIN = A28; |spy_addr3 : OUTPUT_PIN = A29; |spy_addr4 : OUTPUT_PIN = A30; |spy_addr5 : OUTPUT_PIN = B25; |spy_addr6 : OUTPUT_PIN = B26; |spy_addr7 : OUTPUT_PIN = B27; |spy_addr8 : OUTPUT_PIN = B28; |spy_addr9 : OUTPUT_PIN = B29; |spy_addr10 : OUTPUT_PIN = B30; |spy_addr11 : OUTPUT_PIN = C25; |spy_addr12 : OUTPUT_PIN = C26; |spy_addr13 : OUTPUT_PIN = C27; |spy_addr14 : OUTPUT_PIN = C28; |spy_addr15 : OUTPUT_PIN = C29; |spy_addr16 : OUTPUT_PIN = D25; |spy_clk : OUTPUT_PIN = D26; |svt_din1 : INPUT_PIN = A12; |svt_din2 : INPUT_PIN = A13; |svt_din3 : INPUT_PIN = A14; |svt_din4 : INPUT_PIN = A15; |svt_din5 : INPUT_PIN = B10; |svt_din7 : INPUT_PIN = B12; |svt_din8 : INPUT_PIN = B13; |svt_din9 : INPUT_PIN = B14; |svt_din10 : INPUT_PIN = B15; |svt_din11 : INPUT_PIN = C10; |svt_din12 : INPUT_PIN = C11; |svt_din13 : INPUT_PIN = C12; |svt_din14 : INPUT_PIN = C13; |svt_din15 : INPUT_PIN = C14; |svt_din16 : INPUT_PIN = D10; |svt_din17 : INPUT_PIN = D11; |svt_din18 : INPUT_PIN = D12; |svt_din19 : INPUT_PIN = D13; |svt_din20 : INPUT_PIN = D14; |svt_din21 : INPUT_PIN = D15; |svt_din0 : INPUT_PIN = A10; |svt_din6 : INPUT_PIN = B11; DEVICE = EPF10K100ABC600-1; END; DEFAULT_DEVICES BEGIN AUTO_DEVICE = EPF10K250ABC600-1; AUTO_DEVICE = EPF10K250AGC599-1; AUTO_DEVICE = EPF10K130VBC600-2; AUTO_DEVICE = EPF10K130VGC599-2; AUTO_DEVICE = EPF10K100ABC600-1; AUTO_DEVICE = EPF10K100AFC484-1; AUTO_DEVICE = EPF10K100ABC356-1; AUTO_DEVICE = EPF10K100ARC240-1; AUTO_DEVICE = EPF10K50VBC356-1; AUTO_DEVICE = EPF10K50VRC240-1; AUTO_DEVICE = EPF10K30AFC484-1; AUTO_DEVICE = EPF10K30ABC356-1; AUTO_DEVICE = EPF10K30AFC256-1; AUTO_DEVICE = EPF10K30AQC240-1; AUTO_DEVICE = EPF10K30AQC208-1; AUTO_DEVICE = EPF10K30ATC144-1; AUTO_DEVICE = EPF10K10AFC256-1; AUTO_DEVICE = EPF10K10AQC208-1; AUTO_DEVICE = EPF10K10ATC144-1; AUTO_DEVICE = EPF10K10ATC100-1; ASK_BEFORE_ADDING_EXTRA_DEVICES = ON; END; TIMING_POINT BEGIN DEVICE_FOR_TIMING_SYNTHESIS = EPF10K100ABC600-1; |tf_clk : FREQUENCY = 36MHz; MAINTAIN_STABLE_SYNTHESIS = OFF; CUT_ALL_BIDIR = ON; CUT_ALL_CLEAR_PRESET = ON; END; CLIQUE mux1 BEGIN "|fep_cntrl:cntrl1|tf_muxm2:mux1|:214" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:213" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:212" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:211" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:210" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:209" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:208" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:207" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:206" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:205" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:204" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:203" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:202" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:201" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:200" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:199" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:198" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:197" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:196" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:195" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:194" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:193" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:192" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:191" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:190" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:189" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:188" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:187" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:186" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:185" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:184" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:183" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:182" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:181" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:180" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:179" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:178" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:177" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:176" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:175" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:174" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:173" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:172" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:171" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:170" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:169" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:168" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:167" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:166" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:165" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:164" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:163" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:162" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:161" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:160" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:159" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:158" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:157" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:156" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:155" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:154" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:153" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:152" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:151" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:150" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:149" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:148" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:147" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:146" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:145" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:144" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:143" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:142" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:141" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:140" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:139" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:138" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:137" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:136" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:135" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:134" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:133" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:132" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:131" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:130" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:129" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:128" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:127" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:126" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:125" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:124" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:123" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:122" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:121" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:120" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:119" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:118" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:117" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:116" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:115" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:114" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:113" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:112" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:111" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:110" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:109" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:108" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:107" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:106" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:105" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:104" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:103" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:102" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:101" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:100" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:99" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:98" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:97" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:96" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:95" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:94" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:93" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:92" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:91" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:90" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:89" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:88" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:87" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:86" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:85" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:84" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:83" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:82" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:81" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:80" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:79" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:78" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:77" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:76" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:75" : CLIQUE; "|fep_cntrl:cntrl1|tf_muxm2:mux1|:74" : CLIQUE; END; CLIQUE din_lat BEGIN "|fep_dflow:dflow1|:208" : CLIQUE; "|fep_dflow:dflow1|:207" : CLIQUE; "|fep_dflow:dflow1|:206" : CLIQUE; "|fep_dflow:dflow1|:205" : CLIQUE; "|fep_dflow:dflow1|:204" : CLIQUE; "|fep_dflow:dflow1|:203" : CLIQUE; "|fep_dflow:dflow1|:202" : CLIQUE; "|fep_dflow:dflow1|:201" : CLIQUE; "|fep_dflow:dflow1|:200" : CLIQUE; "|fep_dflow:dflow1|:199" : CLIQUE; "|fep_dflow:dflow1|:198" : CLIQUE; "|fep_dflow:dflow1|:197" : CLIQUE; "|fep_dflow:dflow1|:196" : CLIQUE; "|fep_dflow:dflow1|:195" : CLIQUE; "|fep_dflow:dflow1|:194" : CLIQUE; "|fep_dflow:dflow1|:193" : CLIQUE; "|fep_dflow:dflow1|:192" : CLIQUE; "|fep_dflow:dflow1|:191" : CLIQUE; "|fep_dflow:dflow1|:190" : CLIQUE; "|fep_dflow:dflow1|:189" : CLIQUE; "|fep_dflow:dflow1|:188" : CLIQUE; "|fep_dflow:dflow1|:187" : CLIQUE; "|fep_dflow:dflow1|:186" : CLIQUE; END; IGNORED_ASSIGNMENTS BEGIN FIT_IGNORE_TIMING = OFF; IGNORE_PIN_ASSIGNMENTS = OFF; IGNORE_LC_ASSIGNMENTS = OFF; IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF; IGNORE_CLIQUE_ASSIGNMENTS = OFF; IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF; IGNORE_TIMING_ASSIGNMENTS = OFF; IGNORE_CHIP_ASSIGNMENTS = OFF; IGNORE_DEVICE_ASSIGNMENTS = OFF; DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF; END; GLOBAL_PROJECT_DEVICE_OPTIONS BEGIN FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF; ENABLE_CHIP_WIDE_OE = ON; FLEX_CONFIGURATION_EPROM = AUTO; MAX7000AE_ENABLE_JTAG = ON; MAX7000AE_USER_CODE = FFFFFFFF; FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF; FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF; FLEX6000_ENABLE_JTAG = OFF; CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL; MULTIVOLT_IO = OFF; nCEO = UNRESERVED; RESERVED_LCELLS_PERCENT = 0; RESERVED_PINS_PERCENT = 0; SECURITY_BIT = OFF; USER_CLOCK = OFF; AUTO_RESTART = OFF; RELEASE_CLEARS = OFF; ENABLE_DCLK_OUTPUT = OFF; DISABLE_TIME_OUT = OFF; CONFIG_SCHEME = ACTIVE_SERIAL; FLEX8000_ENABLE_JTAG = OFF; DATA0 = RESERVED_TRI_STATED; DATA1_TO_DATA7 = UNRESERVED; nWS_nRS_nCS_CS = UNRESERVED; RDYnBUSY = UNRESERVED; RDCLK = UNRESERVED; SDOUT = RESERVED_DRIVES_OUT; ADD0_TO_ADD12 = UNRESERVED; ADD13 = UNRESERVED; ADD14 = UNRESERVED; ADD15 = UNRESERVED; ADD16 = UNRESERVED; ADD17 = UNRESERVED; CLKUSR = UNRESERVED; ENABLE_CHIP_WIDE_RESET = OFF; ENABLE_INIT_DONE_OUTPUT = OFF; FLEX10K_JTAG_USER_CODE = 7F; CONFIG_SCHEME_10K = PASSIVE_SERIAL; MAX7000S_USER_CODE = FFFF; FLEX10K_ENABLE_LOCK_OUTPUT = OFF; MAX7000S_ENABLE_JTAG = ON; END; GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS BEGIN DEVICE_FAMILY = FLEX10KA; AUTO_FAST_IO = ON; MULTI_LEVEL_SYNTHESIS_MAX9000 = OFF; OPTIMIZE_FOR_SPEED = 5; AUTO_REGISTER_PACKING = OFF; STYLE = NORMAL; ONE_HOT_STATE_MACHINE_ENCODING = OFF; MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF; AUTO_GLOBAL_CLOCK = ON; AUTO_GLOBAL_CLEAR = ON; AUTO_GLOBAL_PRESET = ON; AUTO_GLOBAL_OE = ON; AUTO_OPEN_DRAIN_PINS = ON; AUTO_IMPLEMENT_IN_EAB = OFF; END; COMPILER_PROCESSING_CONFIGURATION BEGIN DESIGN_DOCTOR_RULES = FLEX; SMART_RECOMPILE = ON; OPTIMIZE_TIMING_SNF = OFF; FITTER_SETTINGS = NORMAL; FUNCTIONAL_SNF_EXTRACTOR = OFF; TIMING_SNF_EXTRACTOR = ON; LINKED_SNF_EXTRACTOR = OFF; RPT_FILE_EQUATIONS = ON; RPT_FILE_HIERARCHY = ON; RPT_FILE_LCELL_INTERCONNECT = ON; RPT_FILE_USER_ASSIGNMENTS = ON; GENERATE_AHDL_TDO_FILE = OFF; PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF; DESIGN_DOCTOR = OFF; END; COMPILER_INTERFACES_CONFIGURATION BEGIN EDIF_NETLIST_WRITER = ON; EDIF_OUTPUT_VERSION = 300; EDIF_BUS_DELIMITERS = (); EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = ON; EDIF_OUTPUT_EDC_FILE = "i:\nakaya\svt_official\fep\*.edc"; VHDL_FLATTEN_BUS = OFF; VERILOG_FLATTEN_BUS = OFF; EDIF_TRUNCATE_HIERARCHY_PATH = OFF; VHDL_TRUNCATE_HIERARCHY_PATH = OFF; VERILOG_TRUNCATE_HIERARCHY_PATH = OFF; VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF; VHDL_READER_VERSION = VHDL93; NETLIST_OUTPUT_TIME_SCALE = 0.1ns; EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF; EDIF_FLATTEN_BUS = OFF; EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF; EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF; EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE; EDIF_OUTPUT_USE_EDC = OFF; EDIF_INPUT_USE_LMF2 = OFF; EDIF_INPUT_USE_LMF1 = OFF; EDIF_OUTPUT_GND = GND; EDIF_OUTPUT_VCC = VCC; EDIF_INPUT_GND = GND; EDIF_INPUT_VCC = VCC; EDIF_INPUT_LMF2 = *.lmf; EDIF_INPUT_LMF1 = *.lmf; VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF; VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE; VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE; XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC; XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON; XNF_GENERATE_AHDL_TDX_FILE = ON; VERILOG_NETLIST_WRITER = OFF; VHDL_NETLIST_WRITER = OFF; USE_SYNOPSYS_SYNTHESIS = OFF; SYNOPSYS_COMPILER = DESIGN; SYNOPSYS_DESIGNWARE = OFF; SYNOPSYS_HIERARCHICAL_COMPILATION = ON; SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF; SYNOPSYS_MAPPING_EFFORT = MEDIUM; VHDL_WRITER_VERSION = VHDL87; END; CUSTOM_DESIGN_DOCTOR_RULES BEGIN RIPPLE_CLOCKS = ON; GATED_CLOCKS = ON; MULTI_LEVEL_CLOCKS = ON; MULTI_CLOCK_NETWORKS = ON; STATIC_HAZARDS_BEFORE_SYNTHESIS = ON; STATIC_HAZARDS_AFTER_SYNTHESIS = OFF; PRESET_CLEAR_NETWORKS = ON; ASYNCHRONOUS_INPUTS = ON; DELAY_CHAINS = ON; RACE_CONDITIONS = ON; EXPANDER_NETWORKS = ON; MASTER_RESET = OFF; END; SIMULATOR_CONFIGURATION BEGIN END_TIME = 1.425us; SIMULATION_INPUT_FILE = fep_dout.scf; SETUP_HOLD = ON; USE_DEVICE = OFF; CHECK_OUTPUTS = OFF; OSCILLATION = OFF; OSCILLATION_TIME = 0.0ns; GLITCH = OFF; GLITCH_TIME = 0.0ns; START_TIME = 0.0ns; END; TIMING_ANALYZER_CONFIGURATION BEGIN ANALYSIS_MODE = REGISTERED_PERFORMANCE; |N_hbfifo_rena : DELAY_MATRIX_DESTINATION; |tf_clk : DELAY_MATRIX_SOURCE; |N_fifo_empty1 : DELAY_MATRIX_SOURCE; |N_fifo_empty0 : DELAY_MATRIX_SOURCE; |tf_clk : SETUP_HOLD_SOURCE; |spy_cnt_ena : SETUP_HOLD_SOURCE; "|fep_dflow:dflow1|:179.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|:177.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|:175.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|:173.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|:171.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|:169.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|:167.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|:165.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|:163.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|:161.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|:159.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|:157.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|:155.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|:153.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|:151.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|:149.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|:147.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|:145.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|:143.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|:141.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|:139.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|:137.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|:135.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|:133.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|:131.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|:129.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|:127.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|:59.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|:57.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:137.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:135.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:133.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:131.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:129.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:127.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:125.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:123.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:121.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:119.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:117.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:115.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:113.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:111.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:109.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:107.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:105.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:103.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:101.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:99.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:97.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:95.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:93.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:91.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:89.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:87.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:85.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:83.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:81.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:79.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:77.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:75.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:73.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:71.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:69.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:67.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:65.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:63.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:61.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:59.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:57.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:55.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:53.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:51.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:49.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:47.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:45.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:43.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:41.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:39.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:37.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:35.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:33.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:31.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:29.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|:27.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|zid_out2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|zid_out1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|zid_out0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|zid_in2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|zid_in1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|zid_in0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|xft_valid.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|parity.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_unpack:unpack|lcls.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_18~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_18~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_18~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_18~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_18~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_18~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_17~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_17~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_17~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_17~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_17~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_17~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_16~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_16~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_16~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_16~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_16~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_16~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_15~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_15~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_15~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_15~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_15~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_15~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_14~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_14~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_14~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_14~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_14~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_14~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_13~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_13~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_13~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_13~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_13~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_13~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_12~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_12~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_12~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_12~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_12~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_12~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_11~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_11~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_11~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_11~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_11~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_11~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_10~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_10~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_10~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_10~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_10~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_10~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_9~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_9~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_9~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_9~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_9~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_9~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_8~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_8~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_8~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_8~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_8~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_8~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_7~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_7~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_7~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_7~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_7~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_7~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_6~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_6~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_6~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_6~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_6~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_6~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_5~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_5~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_5~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_5~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_5~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_5~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_4~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_4~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_4~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_4~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_4~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_4~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_3~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_3~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_3~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_3~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_3~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_3~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_2~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_2~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_2~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_2~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_2~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_2~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_1~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_1~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_1~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_1~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_1~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_1~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_0~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_0~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_0~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_0~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_0~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram5|altram:sram|segment0_0~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_8~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_8~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_8~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_8~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_8~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_8~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_7~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_7~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_7~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_7~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_7~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_7~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_6~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_6~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_6~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_6~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_6~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_6~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_5~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_5~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_5~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_5~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_5~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_5~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_4~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_4~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_4~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_4~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_4~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_4~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_3~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_3~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_3~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_3~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_3~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_3~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_2~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_2~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_2~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_2~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_2~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_2~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_1~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_1~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_1~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_1~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_1~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_1~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_0~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_0~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_0~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_0~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_0~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram4|altram:sram|segment0_0~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_8~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_8~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_8~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_8~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_8~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_8~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_7~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_7~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_7~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_7~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_7~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_7~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_6~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_6~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_6~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_6~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_6~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_6~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_5~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_5~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_5~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_5~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_5~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_5~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_4~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_4~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_4~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_4~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_4~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_4~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_3~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_3~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_3~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_3~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_3~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_3~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_2~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_2~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_2~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_2~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_2~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_2~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_1~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_1~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_1~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_1~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_1~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_1~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_0~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_0~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_0~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_0~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_0~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram3|altram:sram|segment0_0~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_7~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_7~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_7~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_7~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_7~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_7~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_6~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_6~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_6~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_6~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_6~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_6~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_5~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_5~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_5~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_5~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_5~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_5~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_4~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_4~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_4~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_4~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_4~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_4~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_3~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_3~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_3~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_3~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_3~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_3~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_2~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_2~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_2~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_2~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_2~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_2~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_1~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_1~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_1~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_1~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_1~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_1~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_0~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_0~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_0~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_0~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_0~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram2|altram:sram|segment0_0~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_8~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_8~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_8~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_8~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_8~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_8~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_7~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_7~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_7~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_7~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_7~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_7~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_6~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_6~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_6~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_6~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_6~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_6~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_5~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_5~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_5~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_5~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_5~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_5~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_4~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_4~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_4~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_4~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_4~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_4~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_3~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_3~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_3~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_3~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_3~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_3~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_2~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_2~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_2~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_2~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_2~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_2~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_1~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_1~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_1~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_1~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_1~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_1~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_0~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_0~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_0~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_0~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_0~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram1|altram:sram|segment0_0~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_8~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_8~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_8~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_8~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_8~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_8~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_7~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_7~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_7~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_7~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_7~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_7~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_6~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_6~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_6~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_6~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_6~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_6~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_5~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_5~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_5~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_5~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_5~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_5~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_4~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_4~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_4~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_4~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_4~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_4~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_3~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_3~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_3~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_3~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_3~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_3~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_2~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_2~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_2~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_2~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_2~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_2~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_1~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_1~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_1~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_1~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_1~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_1~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_0~WE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_0~D.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_0~BE.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_0~A2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_0~A1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_ram:ram|lpm_ram_dq:ram0|altram:sram|segment0_0~A0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|:85.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|:83.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|:81.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|:79.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|:77.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|:75.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|:73.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|:71.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|:69.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|:67.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|:65.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|:63.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|:61.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|:59.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|:57.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|:55.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|:53.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|:51.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|:49.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|:47.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|:45.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|:43.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|:41.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|:39.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|:37.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|:35.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|:33.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|:31.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|:29.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|state1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|state0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|nmly2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|nmly1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|nmly0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|mly32.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|mly31.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|mly30.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|mly22.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|mly21.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|mly20.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|mly12.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|mly11.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|mly10.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|mly02.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|mly01.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|mly00.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|mht32.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|mht31.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|mht30.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|mht22.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|mht21.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|mht20.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|mht12.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|mht11.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|mht10.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|mht02.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|mht01.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|mht00.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|comb4.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|comb3.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|comb2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|comb1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|comb0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|cnt32.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|cnt31.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|cnt30.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|cnt22.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|cnt21.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|cnt20.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|cnt12.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|cnt11.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|cnt10.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|cnt02.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|cnt01.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dout:fepout|cnt00.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|:64.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|:62.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|:60.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|:58.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|:56.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|:54.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|:52.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|:50.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|:48.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|:46.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|:44.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|:42.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|:40.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|:38.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|:36.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|:34.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|:32.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|:30.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|:28.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|:26.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|:24.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|:22.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|:20.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|:18.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|:16.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|:14.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|:12.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|:10.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|:8.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|xftdata.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|nh52.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|nh51.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|nh50.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|nh42.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|nh41.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|nh40.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|nh32.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|nh31.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|nh30.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|nh22.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|nh21.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|nh20.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|nh12.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|nh11.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|nh10.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|nh02.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|nh01.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|nh00.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|ncount2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|ncount1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|ncount0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|ncntold2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|ncntold1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|ncntold0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|lyrold2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|lyrold1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_din:fepin|lyrold0.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dcntrl:dcntrl|:22.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dcntrl:dcntrl|:20.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dcntrl:dcntrl|:18.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dcntrl:dcntrl|state~7.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dcntrl:dcntrl|state~6.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dcntrl:dcntrl|state~5.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dcntrl:dcntrl|state~4.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dcntrl:dcntrl|state~3.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dcntrl:dcntrl|state~2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dcntrl:dcntrl|state~1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|fep_dcntrl:dcntrl|fifo_rena.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|din_lat22.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|din_lat21.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|din_lat20.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|din_lat19.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|din_lat18.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|din_lat17.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|din_lat16.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|din_lat15.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|din_lat14.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|din_lat13.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|din_lat12.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|din_lat11.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|din_lat10.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|din_lat9.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|din_lat8.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|din_lat7.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|din_lat6.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|din_lat5.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|din_lat4.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|din_lat3.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|din_lat2.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|din_lat1.Q" : SETUP_HOLD_DESTINATION; "|fep_dflow:dflow1|din_lat0.Q" : SETUP_HOLD_DESTINATION; |fep_data_lat22.Q : SETUP_HOLD_DESTINATION; |fep_data_lat21.Q : SETUP_HOLD_DESTINATION; |fep_data_lat20.Q : SETUP_HOLD_DESTINATION; |fep_data_lat19.Q : SETUP_HOLD_DESTINATION; |fep_data_lat18.Q : SETUP_HOLD_DESTINATION; |fep_data_lat17.Q : SETUP_HOLD_DESTINATION; |fep_data_lat16.Q : SETUP_HOLD_DESTINATION; |fep_data_lat15.Q : SETUP_HOLD_DESTINATION; |fep_data_lat14.Q : SETUP_HOLD_DESTINATION; |fep_data_lat13.Q : SETUP_HOLD_DESTINATION; |fep_data_lat12.Q : SETUP_HOLD_DESTINATION; |fep_data_lat11.Q : SETUP_HOLD_DESTINATION; |fep_data_lat10.Q : SETUP_HOLD_DESTINATION; |fep_data_lat9.Q : SETUP_HOLD_DESTINATION; |fep_data_lat8.Q : SETUP_HOLD_DESTINATION; |fep_data_lat7.Q : SETUP_HOLD_DESTINATION; |fep_data_lat6.Q : SETUP_HOLD_DESTINATION; |fep_data_lat5.Q : SETUP_HOLD_DESTINATION; |fep_data_lat4.Q : SETUP_HOLD_DESTINATION; |fep_data_lat3.Q : SETUP_HOLD_DESTINATION; |fep_data_lat2.Q : SETUP_HOLD_DESTINATION; |fep_data_lat1.Q : SETUP_HOLD_DESTINATION; |fep_data_lat0.Q : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|tf_counter:cnt|oflow_q.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|tf_counter:cnt|lpm_counter:cnt1~34|f8count:p8c2|QA.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|tf_counter:cnt|lpm_counter:cnt1~34|f8count:p8c1|QH.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|tf_counter:cnt|lpm_counter:cnt1~34|f8count:p8c1|QG.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|tf_counter:cnt|lpm_counter:cnt1~34|f8count:p8c1|QF.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|tf_counter:cnt|lpm_counter:cnt1~34|f8count:p8c1|QE.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|tf_counter:cnt|lpm_counter:cnt1~34|f8count:p8c1|QD.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|tf_counter:cnt|lpm_counter:cnt1~34|f8count:p8c1|QC.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|tf_counter:cnt|lpm_counter:cnt1~34|f8count:p8c1|QB.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|tf_counter:cnt|lpm_counter:cnt1~34|f8count:p8c1|QA.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|tf_counter:cnt|lpm_counter:cnt1~34|f8count:p8c0|QH.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|tf_counter:cnt|lpm_counter:cnt1~34|f8count:p8c0|QG.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|tf_counter:cnt|lpm_counter:cnt1~34|f8count:p8c0|QF.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|tf_counter:cnt|lpm_counter:cnt1~34|f8count:p8c0|QE.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|tf_counter:cnt|lpm_counter:cnt1~34|f8count:p8c0|QD.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|tf_counter:cnt|lpm_counter:cnt1~34|f8count:p8c0|QC.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|tf_counter:cnt|lpm_counter:cnt1~34|f8count:p8c0|QB.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|tf_counter:cnt|lpm_counter:cnt1~34|f8count:p8c0|QA.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|fep_reg:reg1|:106.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|fep_reg:reg1|:104.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|fep_reg:reg1|:102.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|fep_reg:reg1|:100.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|fep_reg:reg1|:98.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|fep_reg:reg1|:86.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|fep_reg:reg1|:84.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|fep_reg:reg1|:82.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|fep_reg:reg1|:80.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|fep_reg:reg1|:78.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|fep_reg:reg1|:76.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|fep_reg:reg1|:74.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|fep_reg:reg1|:72.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|fep_reg:reg1|:70.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|fep_reg:reg1|:68.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|fep_reg:reg1|:66.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|fep_reg:reg1|:64.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|fep_reg:reg1|:62.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|fep_reg:reg1|:60.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|fep_reg:reg1|:58.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|fep_reg:reg1|:56.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|fep_reg:reg1|:54.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|fep_reg:reg1|:52.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|fep_reg:reg1|:50.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|fep_reg:reg1|:48.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|fep_reg:reg1|:46.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|fep_reg:reg1|:44.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|fep_reg:reg1|:42.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|fep_reg:reg1|:40.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|fep_reg:reg1|:38.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|fep_reg:reg1|:36.Q" : SETUP_HOLD_DESTINATION; "|fep_cntrl:cntrl1|fep_reg:reg1|:34.Q" : SETUP_HOLD_DESTINATION; CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF; AUTO_RECALCULATE = OFF; CUT_OFF_IO_PIN_FEEDBACK = ON; CUT_OFF_CLEAR_AND_PRESET_PATHS = ON; LIST_ONLY_LONGEST_PATH = ON; CELL_WIDTH = 18; DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS; INCLUDE_PATHS_GREATER_THAN = OFF; INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns; INCLUDE_PATHS_LESS_THAN = OFF; INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms; REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS; LIST_PATH_COUNT = 10; LIST_PATH_FREQUENCY = 10MHz; END; OTHER_CONFIGURATION BEGIN LAST_MAXPLUS2_VERSION = 9.1; COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,1,1,1,1"; ROW_PINS_LCELL_INSERT = ON; CARRY_OUT_PINS_LCELL_INSERT = OFF; NORMAL_LCELL_INSERT = ON; ORIGINAL_MAXPLUS2_VERSION = 8.1; EXPLICIT_FAMILY = 1; LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100; ROW_PINS_PERCENT = 50; EXP_PER_LCELL_PERCENT = 100; FAN_IN_PER_LCELL_PERCENT = 100; LCELLS_PER_ROW_PERCENT = 100; DEFAULT_9K_EXP_PER_LCELL = 1/2; FLEX_10K_52_COLUMNS = 40; END; DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000 BEGIN CASCADE_CHAIN = IGNORE; CARRY_CHAIN = IGNORE; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = ON; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = ON; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = ON; SUBFACTOR_EXTRACTION = ON; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000 BEGIN CASCADE_CHAIN = IGNORE; CARRY_CHAIN = IGNORE; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = ON; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = ON; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = ON; SUBFACTOR_EXTRACTION = ON; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC BEGIN CASCADE_CHAIN = IGNORE; CARRY_CHAIN = IGNORE; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = 2; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = 32; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = ON; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = ON; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = ON; SUBFACTOR_EXTRACTION = ON; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000 BEGIN CASCADE_CHAIN = IGNORE; CARRY_CHAIN = IGNORE; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = ON; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000 BEGIN CASCADE_CHAIN = IGNORE; CARRY_CHAIN = IGNORE; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = ON; TURBO_BIT = ON; PARALLEL_EXPANDERS = ON; IGNORE_SOFT_BUFFERS = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC BEGIN CASCADE_CHAIN = IGNORE; CARRY_CHAIN = IGNORE; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000 BEGIN DUPLICATE_LOGIC_EXTRACTION = ON; CASCADE_CHAIN = AUTO; CASCADE_CHAIN_LENGTH = 2; CARRY_CHAIN = AUTO; CARRY_CHAIN_LENGTH = 32; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = ON; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; MINIMIZATION = PARTIAL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = OFF; SOFT_BUFFER_INSERTION = OFF; DECOMPOSE_GATES = OFF; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = OFF; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; MINIMIZATION = PARTIAL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = OFF; SOFT_BUFFER_INSERTION = OFF; DECOMPOSE_GATES = OFF; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = OFF; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; MINIMIZATION = PARTIAL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = OFF; SOFT_BUFFER_INSERTION = OFF; DECOMPOSE_GATES = ON; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000 BEGIN CASCADE_CHAIN = MANUAL; CASCADE_CHAIN_LENGTH = 2; CARRY_CHAIN = MANUAL; CARRY_CHAIN_LENGTH = 32; MINIMIZATION = PARTIAL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = ON; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = OFF; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = OFF; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = OFF; END;