--
--  Copyright (C) 1988-1998 Altera Corporation
--  Any megafunction design, and related net list (encrypted or decrypted),
--  support information, device programming or simulation file, and any other
--  associated documentation or information provided by Altera or a partner
--  under Altera's Megafunction Partnership Program may be used only to
--  program PLD devices (but not masked PLD devices) from Altera.  Any other
--  use of such megafunction design, net list, support information, device
--  programming or simulation file, or any other related documentation or
--  information is prohibited for any other purpose, including, but not
--  limited to modification, reverse engineering, de-compiling, or use with
--  any other silicon devices, unless such use is explicitly licensed under
--  a separate agreement with Altera or a megafunction partner.  Title to
--  the intellectual property, including patents, copyrights, trademarks,
--  trade secrets, or maskworks, embodied in any such megafunction design,
--  net list, support information, device programming or simulation file, or
--  any other related documentation or information provided by Altera or a
--  megafunction partner, remains with Altera, the megafunction partner, or
--  their respective licensors.  No other licenses, including any licenses
--  needed under any third party's intellectual property, are provided herein.
--
CHIP opp
BEGIN
	|vme_tap2 :	INPUT_PIN = AR22;
	|N_init_in :	INPUT_PIN = C18;
	|tf_clk :	INPUT_PIN = E18;
	|fitter_done :	INPUT_PIN = AL18;
	|N_tf_clk :	INPUT_PIN = AM18;
	|clkin :	INPUT_PIN = D18;
	|opp_busy :	OUTPUT_PIN = A6;
	|opp_done :	OUTPUT_PIN = A7;
	|fitter_busy :	INPUT_PIN = A8;
	|fepin_busy :	INPUT_PIN = A9;
	|fepout_busy :	INPUT_PIN = A10;
	|fep_eoe :	INPUT_PIN = B7;
	|tffifo_full :	INPUT_PIN = B9;
	|hbfifo_full :	INPUT_PIN = C16;
	|fitc_spare :	INPUT_PIN = C7;
	|opp_spare :	OUTPUT_PIN = C9;
	|fep_spare :	INPUT_PIN = B16;
	|tmod_run :	INPUT_PIN = D7;
	|tmrun_out :	OUTPUT_PIN = D8;
	|N_fifo_empty2 :	INPUT_PIN = D9;
	|tf_din0 :	INPUT_PIN = D10;
	|tf_din1 :	INPUT_PIN = E7;
	|tf_din2 :	INPUT_PIN = E8;
	|tf_din3 :	INPUT_PIN = E9;
	|tf_din4 :	INPUT_PIN = E10;
	|tf_din5 :	INPUT_PIN = A12;
	|tf_din6 :	INPUT_PIN = A13;
	|tf_din7 :	INPUT_PIN = A14;
	|tf_din8 :	INPUT_PIN = A15;
	|tf_din9 :	INPUT_PIN = B10;
	|tf_din10 :	INPUT_PIN = B11;
	|tf_din11 :	INPUT_PIN = B12;
	|tf_din12 :	INPUT_PIN = B13;
	|tf_din13 :	INPUT_PIN = B14;
	|tf_din14 :	INPUT_PIN = B15;
	|tf_din15 :	INPUT_PIN = C10;
	|tf_din16 :	INPUT_PIN = C11;
	|tf_din17 :	INPUT_PIN = C12;
	|tf_din18 :	INPUT_PIN = C13;
	|tf_din19 :	INPUT_PIN = C14;
	|tf_din20 :	INPUT_PIN = D11;
	|tf_din21 :	INPUT_PIN = D12;
	|tf_din22 :	INPUT_PIN = D13;
	|tfout0 :	OUTPUT_PIN = H2;
	|tfout1 :	OUTPUT_PIN = H3;
	|tfout2 :	OUTPUT_PIN = H4;
	|tfout3 :	OUTPUT_PIN = J1;
	|tfout4 :	OUTPUT_PIN = J2;
	|tfout5 :	OUTPUT_PIN = J3;
	|tfout6 :	OUTPUT_PIN = J4;
	|tfout7 :	OUTPUT_PIN = J5;
	|tfout8 :	OUTPUT_PIN = K1;
	|tfout9 :	OUTPUT_PIN = K2;
	|tfout10 :	OUTPUT_PIN = K3;
	|tfout11 :	OUTPUT_PIN = K4;
	|tfout12 :	OUTPUT_PIN = K5;
	|tfout13 :	OUTPUT_PIN = L1;
	|tfout14 :	OUTPUT_PIN = L2;
	|tfout15 :	OUTPUT_PIN = L3;
	|tfout16 :	OUTPUT_PIN = L4;
	|tfout17 :	OUTPUT_PIN = L5;
	|tfout18 :	OUTPUT_PIN = M1;
	|tfout19 :	OUTPUT_PIN = M3;
	|tfout20 :	OUTPUT_PIN = M4;
	|tfout21 :	OUTPUT_PIN = M5;
	|tfout22 :	OUTPUT_PIN = N1;
	|N_dstrobe :	OUTPUT_PIN = N2;
	|ds_valid :	OUTPUT_PIN = N3;
	|ds_valid_led :	OUTPUT_PIN = U1;
	|ds_valid_in :	INPUT_PIN = N4;
	|N_bpfifo_init :	INPUT_PIN = N5;
	|bpfifo_disable :	INPUT_PIN = P1;
	|N_bpfifo_wena :	OUTPUT_PIN = P2;
	|bpfifo_spare0 :	OUTPUT_PIN = P3;
	|bpfifo_spare1 :	OUTPUT_PIN = P4;
	|clkout1 :	OUTPUT_PIN = D17;
	|clkout2 :	OUTPUT_PIN = U4;
	|N_clkout :	OUTPUT_PIN = E17;
	|spy_clk_in :	INPUT_PIN = AG1;
	|t2clk :	INPUT_PIN = AG2;
	|spy_cnt_ena :	INPUT_PIN = AH3;
	|spy_ena_out :	OUTPUT_PIN = AH4;
	|N_spy_wena :	OUTPUT_PIN = AH1;
	|N_spy_oena :	OUTPUT_PIN = AH2;
	|spy_addr0 :	OUTPUT_PIN = AG3;
	|spy_addr1 :	OUTPUT_PIN = AG4;
	|spy_addr2 :	OUTPUT_PIN = AF1;
	|spy_addr3 :	OUTPUT_PIN = AF2;
	|spy_addr4 :	OUTPUT_PIN = AF3;
	|spy_addr5 :	OUTPUT_PIN = AF4;
	|spy_addr6 :	OUTPUT_PIN = AF5;
	|spy_addr7 :	OUTPUT_PIN = AE1;
	|spy_addr8 :	OUTPUT_PIN = AE2;
	|spy_addr9 :	OUTPUT_PIN = AE3;
	|spy_addr10 :	OUTPUT_PIN = AE5;
	|spy_addr11 :	OUTPUT_PIN = AD1;
	|spy_addr12 :	OUTPUT_PIN = AD2;
	|spy_addr13 :	OUTPUT_PIN = AD3;
	|spy_addr14 :	OUTPUT_PIN = AD4;
	|spy_addr15 :	OUTPUT_PIN = AD5;
	|spy_addr16 :	OUTPUT_PIN = AC1;
	|spy_clk :	OUTPUT_PIN = AJ1;
	|spy_data0 :	BIDIR_PIN = AC2;
	|spy_data1 :	BIDIR_PIN = AC3;
	|spy_data2 :	BIDIR_PIN = AC4;
	|spy_data3 :	BIDIR_PIN = AC5;
	|spy_data4 :	BIDIR_PIN = AB1;
	|spy_data5 :	BIDIR_PIN = AB2;
	|spy_data6 :	BIDIR_PIN = AB3;
	|spy_data7 :	BIDIR_PIN = AB4;
	|spy_data8 :	BIDIR_PIN = AA1;
	|spy_data9 :	BIDIR_PIN = AA2;
	|spy_data10 :	BIDIR_PIN = AA3;
	|spy_data11 :	BIDIR_PIN = AA4;
	|spy_data12 :	BIDIR_PIN = AA5;
	|spy_data13 :	BIDIR_PIN = Y1;
	|spy_data14 :	BIDIR_PIN = Y3;
	|spy_data15 :	BIDIR_PIN = Y4;
	|spy_data16 :	BIDIR_PIN = Y5;
	|spy_data17 :	BIDIR_PIN = W1;
	|spy_data18 :	BIDIR_PIN = W2;
	|spy_data19 :	BIDIR_PIN = W3;
	|spy_data20 :	BIDIR_PIN = W4;
	|spy_data21 :	BIDIR_PIN = W5;
	|spy_data22 :	BIDIR_PIN = V1;
	|spy_data23 :	BIDIR_PIN = V2;
	|spy_data24 :	BIDIR_PIN = V3;
	|spy_data25 :	BIDIR_PIN = V4;
	|hit0 :	INPUT_PIN = A21;
	|hit1 :	INPUT_PIN = A22;
	|hit2 :	INPUT_PIN = A23;
	|hit3 :	INPUT_PIN = A24;
	|hit4 :	INPUT_PIN = A25;
	|hit5 :	INPUT_PIN = A26;
	|hit6 :	INPUT_PIN = A28;
	|hit7 :	INPUT_PIN = A29;
	|hit8 :	INPUT_PIN = A30;
	|hit9 :	INPUT_PIN = B19;
	|hit10 :	INPUT_PIN = B20;
	|hit11 :	INPUT_PIN = B21;
	|hit12 :	INPUT_PIN = B22;
	|hit13 :	INPUT_PIN = B23;
	|hit14 :	INPUT_PIN = B24;
	|hit15 :	INPUT_PIN = B25;
	|hit16 :	INPUT_PIN = B26;
	|hit17 :	INPUT_PIN = B27;
	|hit18 :	INPUT_PIN = B28;
	|hit19 :	INPUT_PIN = B29;
	|hit20 :	INPUT_PIN = B30;
	|hit21 :	INPUT_PIN = C19;
	|hit22 :	INPUT_PIN = C20;
	|hit23 :	INPUT_PIN = C21;
	|hit24 :	INPUT_PIN = C22;
	|hit25 :	INPUT_PIN = C24;
	|hit26 :	INPUT_PIN = C25;
	|hit27 :	INPUT_PIN = C26;
	|hit28 :	INPUT_PIN = C27;
	|hit29 :	INPUT_PIN = C28;
	|hit30 :	INPUT_PIN = C29;
	|hit31 :	INPUT_PIN = D19;
	|hit32 :	INPUT_PIN = D20;
	|hit33 :	INPUT_PIN = D21;
	|hit34 :	INPUT_PIN = D22;
	|hit35 :	INPUT_PIN = D23;
	|hit36 :	INPUT_PIN = D25;
	|hit37 :	INPUT_PIN = D26;
	|hit38 :	INPUT_PIN = D27;
	|hit39 :	INPUT_PIN = D28;
	|hit43 :	INPUT_PIN = D29;
	|hit44 :	INPUT_PIN = E19;
	|hit45 :	INPUT_PIN = E20;
	|hit46 :	INPUT_PIN = E21;
	|hit47 :	INPUT_PIN = E22;
	|hit48 :	INPUT_PIN = E23;
	|hit49 :	INPUT_PIN = E24;
	|hit50 :	INPUT_PIN = E25;
	|hit51 :	INPUT_PIN = E26;
	|hit59 :	INPUT_PIN = E27;
	|hit60 :	INPUT_PIN = E28;
	|hit61 :	INPUT_PIN = E29;
	|hit62 :	INPUT_PIN = A17;
	|hit63 :	INPUT_PIN = B17;
	|hitlyr0 :	INPUT_PIN = H32;
	|hitlyr1 :	INPUT_PIN = H33;
	|hitlyr2 :	INPUT_PIN = H34;
	|hitlyr3 :	INPUT_PIN = H35;
	|hitlyr4 :	INPUT_PIN = J31;
	|hitlyr5 :	INPUT_PIN = J32;
	|zsvx0 :	INPUT_PIN = J33;
	|zsvx1 :	INPUT_PIN = J34;
	|zsvx2 :	INPUT_PIN = J35;
	|zsvx3 :	INPUT_PIN = K31;
	|zsvx4 :	INPUT_PIN = K33;
	|zsvx5 :	INPUT_PIN = K34;
	|sector0 :	INPUT_PIN = K35;
	|sector1 :	INPUT_PIN = L31;
	|sector2 :	INPUT_PIN = L32;
	|sector3 :	INPUT_PIN = L33;
	|road0 :	INPUT_PIN = L34;
	|road1 :	INPUT_PIN = L35;
	|road2 :	INPUT_PIN = M31;
	|road3 :	INPUT_PIN = M32;
	|road4 :	INPUT_PIN = M33;
	|road5 :	INPUT_PIN = M34;
	|road6 :	INPUT_PIN = M35;
	|road7 :	INPUT_PIN = N31;
	|road8 :	INPUT_PIN = N32;
	|road9 :	INPUT_PIN = N33;
	|road10 :	INPUT_PIN = N35;
	|road11 :	INPUT_PIN = P31;
	|road12 :	INPUT_PIN = P32;
	|road13 :	INPUT_PIN = P33;
	|road14 :	INPUT_PIN = P34;
	|parity_err :	INPUT_PIN = B8;
	|par_a0 :	INPUT_PIN = R31;
	|par_a1 :	INPUT_PIN = R32;
	|par_a2 :	INPUT_PIN = R33;
	|par_a3 :	INPUT_PIN = R34;
	|par_a4 :	INPUT_PIN = R35;
	|par_a5 :	INPUT_PIN = T31;
	|par_a6 :	INPUT_PIN = T32;
	|par_a7 :	INPUT_PIN = T33;
	|par_a8 :	INPUT_PIN = T34;
	|par_a9 :	INPUT_PIN = U31;
	|par_a10 :	INPUT_PIN = U32;
	|par_a11 :	INPUT_PIN = U33;
	|par_a12 :	INPUT_PIN = U34;
	|par_a13 :	INPUT_PIN = U35;
	|par_b0 :	INPUT_PIN = V31;
	|par_b1 :	INPUT_PIN = V33;
	|par_b2 :	INPUT_PIN = V34;
	|par_b3 :	INPUT_PIN = V35;
	|par_b4 :	INPUT_PIN = W31;
	|par_b5 :	INPUT_PIN = W32;
	|par_b6 :	INPUT_PIN = W33;
	|par_b7 :	INPUT_PIN = W34;
	|par_b8 :	INPUT_PIN = W35;
	|par_b9 :	INPUT_PIN = Y31;
	|par_b10 :	INPUT_PIN = Y32;
	|par_b11 :	INPUT_PIN = Y33;
	|par_b12 :	INPUT_PIN = Y34;
	|par_b13 :	INPUT_PIN = Y35;
	|par_c0 :	INPUT_PIN = AA31;
	|par_c1 :	INPUT_PIN = AA32;
	|par_c2 :	INPUT_PIN = AA34;
	|par_c3 :	INPUT_PIN = AA35;
	|par_c4 :	INPUT_PIN = AE31;
	|par_c5 :	INPUT_PIN = AE32;
	|par_c6 :	INPUT_PIN = AF31;
	|par_c7 :	INPUT_PIN = AF33;
	|par_c8 :	INPUT_PIN = AF34;
	|par_c9 :	INPUT_PIN = AF35;
	|par_c10 :	INPUT_PIN = AG31;
	|par_c11 :	INPUT_PIN = AG32;
	|par_c12 :	INPUT_PIN = AG33;
	|par_c13 :	INPUT_PIN = AG34;
	|chi_a0 :	INPUT_PIN = AG35;
	|chi_a1 :	INPUT_PIN = AH31;
	|chi_a2 :	INPUT_PIN = AH32;
	|chi_a3 :	INPUT_PIN = AH33;
	|chi_a4 :	INPUT_PIN = AH34;
	|chi_a5 :	INPUT_PIN = AH35;
	|chi_a6 :	INPUT_PIN = AJ31;
	|chi_a7 :	INPUT_PIN = AJ32;
	|chi_a8 :	INPUT_PIN = AJ33;
	|chi_a9 :	INPUT_PIN = AJ34;
	|chi_a10 :	INPUT_PIN = AJ35;
	|chi_a11 :	INPUT_PIN = AK32;
	|chi_a12 :	INPUT_PIN = AK33;
	|chi_a13 :	INPUT_PIN = AK34;
	|chi_b0 :	INPUT_PIN = AL32;
	|chi_b1 :	INPUT_PIN = AL33;
	|chi_b2 :	INPUT_PIN = AL34;
	|chi_b3 :	INPUT_PIN = AL35;
	|chi_b4 :	INPUT_PIN = AM33;
	|chi_b5 :	INPUT_PIN = AM34;
	|chi_b6 :	INPUT_PIN = AM35;
	|chi_b7 :	INPUT_PIN = AL28;
	|chi_b8 :	INPUT_PIN = AL29;
	|chi_b9 :	INPUT_PIN = AL26;
	|chi_b10 :	INPUT_PIN = AL27;
	|chi_b11 :	INPUT_PIN = AM27;
	|chi_b12 :	INPUT_PIN = AM28;
	|chi_b13 :	INPUT_PIN = AM29;
	|chi_c0 :	INPUT_PIN = AR24;
	|chi_c1 :	INPUT_PIN = AR25;
	|chi_c2 :	INPUT_PIN = AP22;
	|chi_c3 :	INPUT_PIN = AP23;
	|chi_c4 :	INPUT_PIN = AP25;
	|chi_c5 :	INPUT_PIN = AN26;
	|chi_c6 :	INPUT_PIN = AN27;
	|chi_c7 :	INPUT_PIN = AN28;
	|chi_c8 :	INPUT_PIN = AN29;
	|chi_c9 :	INPUT_PIN = AP26;
	|chi_c10 :	INPUT_PIN = AP27;
	|chi_c11 :	INPUT_PIN = AP28;
	|chi_c12 :	INPUT_PIN = AP29;
	|chi_c13 :	INPUT_PIN = AR29;
	|oflow_phi0 :	INPUT_PIN = AR28;
	|oflow_phi1 :	INPUT_PIN = AR27;
	|oflow_phi2 :	INPUT_PIN = AR26;
	|oflow_phi3 :	INPUT_PIN = AL21;
	|oflow_phi4 :	INPUT_PIN = AL22;
	|oflow_phi5 :	INPUT_PIN = AL23;
	|oflow_cvr0 :	INPUT_PIN = AL24;
	|oflow_cvr1 :	INPUT_PIN = AL25;
	|oflow_cvr2 :	INPUT_PIN = AM21;
	|oflow_cvr3 :	INPUT_PIN = AM22;
	|oflow_cvr4 :	INPUT_PIN = AM23;
	|oflow_cvr5 :	INPUT_PIN = AM24;
	|oflow_result0 :	INPUT_PIN = AM25;
	|oflow_result1 :	INPUT_PIN = AN21;
	|oflow_result2 :	INPUT_PIN = AN22;
	|oflow_result3 :	INPUT_PIN = AN23;
	|oflow_result4 :	INPUT_PIN = AN24;
	|oflow_result5 :	INPUT_PIN = AN25;
	|oflow_cmb :	INPUT_PIN = D16;
	|outorder :	INPUT_PIN = AN18;
	|oflow_lyr :	INPUT_PIN = C17;
	|oflow_hit :	INPUT_PIN = V5;
	|uflow_hit :	INPUT_PIN = E16;
	|N_freeze_in :	INPUT_PIN = E11;
	|N_freeze :	OUTPUT_PIN = E13;
	|N_init :	OUTPUT_PIN = D14;
	|init :	OUTPUT_PIN = E14;
	|run_mode :	OUTPUT_PIN = A16;
	|tst_mode0 :	OUTPUT_PIN = D15;
	|tst_mode1 :	OUTPUT_PIN = E15;
	|opp_state0 :	OUTPUT_PIN = T2;
	|opp_state1 :	OUTPUT_PIN = T3;
	|opp_state2 :	OUTPUT_PIN = T4;
	|opp_state3 :	OUTPUT_PIN = T5;
	|hold_opp :	INPUT_PIN = R1;
	|src_config :	INPUT_PIN = R2;
	|N_svtspare_in :	INPUT_PIN = R3;
	|N_svterr :	OUTPUT_PIN = R5;
	|N_cdferr :	OUTPUT_PIN = T1;
	|N_modsel :	INPUT_PIN = AR14;
	|vme_wrt :	INPUT_PIN = Ar15;
	|vme_tap0 :	INPUT_PIN = AR16;
	|vme_tap1 :	INPUT_PIN = AR17;
	|vme_tap3 :	INPUT_PIN = AR20;
	|vme_tap4 :	INPUT_PIN = AR21;
	|vme_addr0 :	INPUT_PIN = AL7;
	|vme_addr1 :	INPUT_PIN = AL8;
	|vme_addr2 :	INPUT_PIN = AL9;
	|vme_addr3 :	INPUT_PIN = AL10;
	|vme_addr4 :	INPUT_PIN = AL11;
	|vme_addr5 :	INPUT_PIN = AM7;
	|vme_addr6 :	INPUT_PIN = AM8;
	|vme_addr7 :	INPUT_PIN = AM9;
	|vme_addr8 :	INPUT_PIN = AM10;
	|vme_addr9 :	INPUT_PIN = AM11;
	|vme_addr10 :	INPUT_PIN = AM12;
	|vme_addr11 :	INPUT_PIN = AN7;
	|vme_addr12 :	INPUT_PIN = AN9;
	|vme_addr13 :	INPUT_PIN = AN10;
	|vme_addr14 :	INPUT_PIN = AN11;
	|vme_addr15 :	INPUT_PIN = AN12;
	|vme_addr16 :	INPUT_PIN = AP7;
	|vme_addr17 :	INPUT_PIN = AP8;
	|vme_addr18 :	INPUT_PIN = AP9;
	|vme_addr19 :	INPUT_PIN = AP10;
	|vme_addr20 :	INPUT_PIN = AP11;
	|vme_addr21 :	INPUT_PIN = AP12;
	|vme_addr22 :	INPUT_PIN = AR6;
	|vme_addr23 :	INPUT_PIN = AR7;
	|vme_addr24 :	INPUT_PIN = AR8;
	|vme_data0 :	BIDIR_PIN = AR9;
	|vme_data1 :	BIDIR_PIN = AR10;
	|vme_data2 :	BIDIR_PIN = AL13;
	|vme_data3 :	BIDIR_PIN = AL14;
	|vme_data4 :	BIDIR_PIN = AL15;
	|vme_data5 :	BIDIR_PIN = AL16;
	|vme_data6 :	BIDIR_PIN = AL17;
	|vme_data7 :	BIDIR_PIN = AL19;
	|vme_data8 :	BIDIR_PIN = AL20;
	|vme_data9 :	BIDIR_PIN = AM13;
	|vme_data10 :	BIDIR_PIN = AM14;
	|vme_data11 :	BIDIR_PIN = AM15;
	|vme_data12 :	BIDIR_PIN = AM16;
	|vme_data13 :	BIDIR_PIN = AM17;
	|vme_data14 :	BIDIR_PIN = AM20;
	|vme_data15 :	BIDIR_PIN = AN13;
	|vme_data16 :	BIDIR_PIN = AN14;
	|vme_data17 :	BIDIR_PIN = AN16;
	|vme_data18 :	BIDIR_PIN = AN17;
	|vme_data19 :	BIDIR_PIN = AP21;
	|vme_data20 :	BIDIR_PIN = AN19;
	|vme_data21 :	BIDIR_PIN = AN20;
	|vme_data22 :	BIDIR_PIN = AP13;
	|vme_data23 :	BIDIR_PIN = AP14;
	|vme_data24 :	BIDIR_PIN = AP15;
	|vme_data25 :	BIDIR_PIN = AP16;
	|vme_data26 :	BIDIR_PIN = AP17;
	|vme_data27 :	BIDIR_PIN = AP18;
	|vme_data28 :	BIDIR_PIN = AP19;
	|vme_data29 :	BIDIR_PIN = AP20;
	|vme_data30 :	BIDIR_PIN = AR12;
	|vme_data31 :	BIDIR_PIN = AR13;
	DEVICE = EPF10K100ABC600-1;
END;

DEFAULT_DEVICES
BEGIN
	AUTO_DEVICE = EPF10K250ABC600-1;
	AUTO_DEVICE = EPF10K250AGC599-1;
	AUTO_DEVICE = EPF10K130VBC600-2;
	AUTO_DEVICE = EPF10K130VGC599-2;
	AUTO_DEVICE = EPF10K100ABC600-1;
	AUTO_DEVICE = EPF10K100ABC356-1;
	AUTO_DEVICE = EPF10K100ARC240-1;
	AUTO_DEVICE = EPF10K50VBC356-1;
	AUTO_DEVICE = EPF10K50VRC240-1;
	AUTO_DEVICE = EPF10K30AQC240-1;
	AUTO_DEVICE = EPF10K30AQC208-1;
	AUTO_DEVICE = EPF10K30ATC144-1;
	AUTO_DEVICE = EPF10K10AQC208-1;
	AUTO_DEVICE = EPF10K10ATC144-1;
	ASK_BEFORE_ADDING_EXTRA_DEVICES = ON;
END;

TIMING_POINT
BEGIN
	DEVICE_FOR_TIMING_SYNTHESIS = EPF10K100ABC600-1;
	|tf_clk :	FREQUENCY = 36MHz;
	MAINTAIN_STABLE_SYNTHESIS = OFF;
	CUT_ALL_CLEAR_PRESET = ON;
	CUT_ALL_BIDIR = ON;
END;

IGNORED_ASSIGNMENTS
BEGIN
	IGNORE_TIMING_ASSIGNMENTS = OFF;
	IGNORE_PIN_ASSIGNMENTS = OFF;
	FIT_IGNORE_TIMING = OFF;
	IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF;
	DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF;
	IGNORE_DEVICE_ASSIGNMENTS = OFF;
	IGNORE_LC_ASSIGNMENTS = OFF;
	IGNORE_CHIP_ASSIGNMENTS = OFF;
	IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF;
	IGNORE_CLIQUE_ASSIGNMENTS = OFF;
END;

GLOBAL_PROJECT_DEVICE_OPTIONS
BEGIN
	FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
	ENABLE_CHIP_WIDE_OE = ON;
	FLEX_CONFIGURATION_EPROM = AUTO;
	MAX7000AE_ENABLE_JTAG = ON;
	MAX7000AE_USER_CODE = FFFFFFFF;
	FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
	FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
	FLEX6000_ENABLE_JTAG = OFF;
	CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL;
	MULTIVOLT_IO = OFF;
	nCEO = UNRESERVED;
	MAX7000S_ENABLE_JTAG = ON;
	FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
	MAX7000S_USER_CODE = FFFF;
	CONFIG_SCHEME_10K = PASSIVE_SERIAL;
	FLEX10K_JTAG_USER_CODE = 7F;
	ENABLE_INIT_DONE_OUTPUT = OFF;
	ENABLE_CHIP_WIDE_RESET = OFF;
	CLKUSR = UNRESERVED;
	ADD17 = UNRESERVED;
	ADD16 = UNRESERVED;
	ADD15 = UNRESERVED;
	ADD14 = UNRESERVED;
	ADD13 = UNRESERVED;
	ADD0_TO_ADD12 = UNRESERVED;
	SDOUT = RESERVED_DRIVES_OUT;
	RDCLK = UNRESERVED;
	RDYnBUSY = UNRESERVED;
	nWS_nRS_nCS_CS = UNRESERVED;
	DATA1_TO_DATA7 = UNRESERVED;
	DATA0 = RESERVED_TRI_STATED;
	FLEX8000_ENABLE_JTAG = OFF;
	CONFIG_SCHEME = ACTIVE_SERIAL;
	DISABLE_TIME_OUT = OFF;
	ENABLE_DCLK_OUTPUT = OFF;
	RELEASE_CLEARS = OFF;
	AUTO_RESTART = OFF;
	USER_CLOCK = OFF;
	SECURITY_BIT = OFF;
	RESERVED_PINS_PERCENT = 0;
	RESERVED_LCELLS_PERCENT = 0;
END;

GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS
BEGIN
	AUTO_REGISTER_PACKING = OFF;
	AUTO_OPEN_DRAIN_PINS = ON;
	AUTO_FAST_IO = ON;
	OPTIMIZE_FOR_SPEED = 10;
	DEVICE_FAMILY = FLEX10KA;
	ONE_HOT_STATE_MACHINE_ENCODING = OFF;
	STYLE = NORMAL;
	AUTO_IMPLEMENT_IN_EAB = OFF;
	AUTO_GLOBAL_OE = ON;
	AUTO_GLOBAL_PRESET = ON;
	AUTO_GLOBAL_CLEAR = ON;
	AUTO_GLOBAL_CLOCK = ON;
	MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF;
	MULTI_LEVEL_SYNTHESIS_MAX9000 = OFF;
END;

COMPILER_PROCESSING_CONFIGURATION
BEGIN
	FITTER_SETTINGS = NORMAL;
	OPTIMIZE_TIMING_SNF = ON;
	FUNCTIONAL_SNF_EXTRACTOR = OFF;
	DESIGN_DOCTOR = OFF;
	DESIGN_DOCTOR_RULES = FLEX;
	PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF;
	GENERATE_AHDL_TDO_FILE = OFF;
	RPT_FILE_USER_ASSIGNMENTS = ON;
	RPT_FILE_LCELL_INTERCONNECT = ON;
	RPT_FILE_HIERARCHY = ON;
	RPT_FILE_EQUATIONS = ON;
	LINKED_SNF_EXTRACTOR = OFF;
	TIMING_SNF_EXTRACTOR = ON;
	SMART_RECOMPILE = ON;
END;

COMPILER_INTERFACES_CONFIGURATION
BEGIN
	EDIF_NETLIST_WRITER = ON;
	EDIF_OUTPUT_VERSION = 300;
	EDIF_BUS_DELIMITERS = ();
	EDIF_FLATTEN_BUS = OFF;
	EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
	VHDL_NETLIST_WRITER = OFF;
	VHDL_GENERATE_CONFIGURATION_DECLARATION = ON;
	VHDL_TRUNCATE_HIERARCHY_PATH = ON;
	EDIF_INPUT_USE_LMF1 = ON;
	EDIF_INPUT_LMF2 = "e:\nakaya\svt_official\opp\*.lmf";
	EDIF_INPUT_LMF1 = exemplar.lmf;
	EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = ON;
	EDIF_OUTPUT_EDC_FILE = "e:\nakaya\svt_official\opp\*.edc";
	VHDL_FLATTEN_BUS = OFF;
	VERILOG_FLATTEN_BUS = OFF;
	EDIF_TRUNCATE_HIERARCHY_PATH = OFF;
	VERILOG_TRUNCATE_HIERARCHY_PATH = OFF;
	VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
	VHDL_WRITER_VERSION = VHDL87;
	SYNOPSYS_MAPPING_EFFORT = MEDIUM;
	SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF;
	SYNOPSYS_HIERARCHICAL_COMPILATION = ON;
	SYNOPSYS_DESIGNWARE = OFF;
	SYNOPSYS_COMPILER = DESIGN;
	USE_SYNOPSYS_SYNTHESIS = OFF;
	VERILOG_NETLIST_WRITER = OFF;
	XNF_GENERATE_AHDL_TDX_FILE = ON;
	XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON;
	XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC;
	VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE;
	VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE;
	EDIF_INPUT_VCC = VCC;
	EDIF_INPUT_GND = GND;
	EDIF_OUTPUT_VCC = VCC;
	EDIF_OUTPUT_GND = GND;
	EDIF_INPUT_USE_LMF2 = OFF;
	EDIF_OUTPUT_USE_EDC = OFF;
	EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE;
	EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF;
	EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF;
	NETLIST_OUTPUT_TIME_SCALE = 0.1ns;
	VHDL_READER_VERSION = VHDL93;
END;

CUSTOM_DESIGN_DOCTOR_RULES
BEGIN
	MASTER_RESET = OFF;
	EXPANDER_NETWORKS = ON;
	RACE_CONDITIONS = ON;
	DELAY_CHAINS = ON;
	ASYNCHRONOUS_INPUTS = ON;
	PRESET_CLEAR_NETWORKS = ON;
	STATIC_HAZARDS_AFTER_SYNTHESIS = OFF;
	STATIC_HAZARDS_BEFORE_SYNTHESIS = ON;
	MULTI_CLOCK_NETWORKS = ON;
	MULTI_LEVEL_CLOCKS = ON;
	GATED_CLOCKS = ON;
	RIPPLE_CLOCKS = ON;
END;

SIMULATOR_CONFIGURATION
BEGIN
	END_TIME = 1.0us;
	SIMULATION_INPUT_FILE = opp_vme.scf;
	SETUP_HOLD = ON;
	START_TIME = 0.0ns;
	GLITCH_TIME = 0.0ns;
	GLITCH = OFF;
	OSCILLATION_TIME = 0.0ns;
	OSCILLATION = OFF;
	CHECK_OUTPUTS = OFF;
	USE_DEVICE = OFF;
END;

TIMING_ANALYZER_CONFIGURATION
BEGIN
	ANALYSIS_MODE = DELAY_MATRIX;
	|tf_clk :	SETUP_HOLD_SOURCE;
	|spy_data25 :	SETUP_HOLD_SOURCE;
	|spy_data24 :	SETUP_HOLD_SOURCE;
	|spy_data23 :	SETUP_HOLD_SOURCE;
	|spy_data22 :	SETUP_HOLD_SOURCE;
	|spy_data21 :	SETUP_HOLD_SOURCE;
	|spy_data20 :	SETUP_HOLD_SOURCE;
	|spy_data19 :	SETUP_HOLD_SOURCE;
	|spy_data18 :	SETUP_HOLD_SOURCE;
	|spy_data17 :	SETUP_HOLD_SOURCE;
	|spy_data16 :	SETUP_HOLD_SOURCE;
	|spy_data15 :	SETUP_HOLD_SOURCE;
	|spy_data14 :	SETUP_HOLD_SOURCE;
	|spy_data13 :	SETUP_HOLD_SOURCE;
	|spy_data12 :	SETUP_HOLD_SOURCE;
	|spy_data11 :	SETUP_HOLD_SOURCE;
	|spy_data10 :	SETUP_HOLD_SOURCE;
	|spy_data9 :	SETUP_HOLD_SOURCE;
	|spy_data8 :	SETUP_HOLD_SOURCE;
	|spy_data7 :	SETUP_HOLD_SOURCE;
	|spy_data6 :	SETUP_HOLD_SOURCE;
	|spy_data5 :	SETUP_HOLD_SOURCE;
	|spy_data4 :	SETUP_HOLD_SOURCE;
	|spy_data3 :	SETUP_HOLD_SOURCE;
	|spy_data2 :	SETUP_HOLD_SOURCE;
	|spy_data1 :	SETUP_HOLD_SOURCE;
	|spy_data0 :	SETUP_HOLD_SOURCE;
	|spy_cnt_ena :	SETUP_HOLD_SOURCE;
	|fitter_done :	SETUP_HOLD_SOURCE;
	|fitter_busy :	SETUP_HOLD_SOURCE;
	|fepin_busy :	SETUP_HOLD_SOURCE;
	|fep_eoe :	SETUP_HOLD_SOURCE;
	|spy_clk :	DELAY_MATRIX_DESTINATION;
	|drv_ena :	DELAY_MATRIX_DESTINATION;
	|t2clk :	DELAY_MATRIX_SOURCE;
	CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF;
	LIST_PATH_FREQUENCY = 10MHz;
	LIST_PATH_COUNT = 10;
	REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS;
	INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms;
	INCLUDE_PATHS_LESS_THAN = OFF;
	INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns;
	INCLUDE_PATHS_GREATER_THAN = OFF;
	DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS;
	CELL_WIDTH = 18;
	LIST_ONLY_LONGEST_PATH = ON;
	CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
	CUT_OFF_IO_PIN_FEEDBACK = ON;
	AUTO_RECALCULATE = OFF;
END;

OTHER_CONFIGURATION
BEGIN
	LAST_MAXPLUS2_VERSION = 9.1;
	COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,1,1,1,1";
	ROW_PINS_LCELL_INSERT = ON;
	CARRY_OUT_PINS_LCELL_INSERT = OFF;
	NORMAL_LCELL_INSERT = ON;
	LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100;
	FLEX_10K_52_COLUMNS = 40;
	DEFAULT_9K_EXP_PER_LCELL = 1/2;
	LCELLS_PER_ROW_PERCENT = 100;
	FAN_IN_PER_LCELL_PERCENT = 100;
	EXP_PER_LCELL_PERCENT = 100;
	ROW_PINS_PERCENT = 50;
	ORIGINAL_MAXPLUS2_VERSION = 8.1;
	EXPLICIT_FAMILY = 1;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000
BEGIN
	REGISTER_OPTIMIZATION = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = ON;
	SUBFACTOR_EXTRACTION = ON;
	REFACTORIZATION = ON;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = ON;
	REDUCE_LOGIC = ON;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	IGNORE_SOFT_BUFFERS = OFF;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = OFF;
	XOR_SYNTHESIS = ON;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = FULL;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000
BEGIN
	REGISTER_OPTIMIZATION = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = ON;
	SUBFACTOR_EXTRACTION = ON;
	REFACTORIZATION = ON;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = ON;
	REDUCE_LOGIC = ON;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	IGNORE_SOFT_BUFFERS = OFF;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = ON;
	XOR_SYNTHESIS = ON;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = FULL;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC
BEGIN
	REGISTER_OPTIMIZATION = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = OFF;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	IGNORE_SOFT_BUFFERS = OFF;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = ON;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = FULL;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000
BEGIN
	REGISTER_OPTIMIZATION = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = ON;
	SUBFACTOR_EXTRACTION = ON;
	REFACTORIZATION = ON;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = ON;
	REDUCE_LOGIC = ON;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = OFF;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = FULL;
	CARRY_CHAIN_LENGTH = 32;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = 2;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000
BEGIN
	REGISTER_OPTIMIZATION = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = ON;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = ON;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	IGNORE_SOFT_BUFFERS = OFF;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = OFF;
	XOR_SYNTHESIS = ON;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = FULL;
	CARRY_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000
BEGIN
	REGISTER_OPTIMIZATION = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = ON;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = ON;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	IGNORE_SOFT_BUFFERS = OFF;
	PARALLEL_EXPANDERS = ON;
	TURBO_BIT = ON;
	XOR_SYNTHESIS = ON;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = FULL;
	CARRY_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC
BEGIN
	REGISTER_OPTIMIZATION = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = OFF;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	IGNORE_SOFT_BUFFERS = OFF;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = ON;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = FULL;
	CARRY_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000
BEGIN
	REGISTER_OPTIMIZATION = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = ON;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = ON;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	IGNORE_SOFT_BUFFERS = ON;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = OFF;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = FULL;
	CARRY_CHAIN_LENGTH = 32;
	CARRY_CHAIN = AUTO;
	CASCADE_CHAIN_LENGTH = 2;
	CASCADE_CHAIN = AUTO;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000
BEGIN
	REGISTER_OPTIMIZATION = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = OFF;
	MULTI_LEVEL_FACTORING = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = OFF;
	DECOMPOSE_GATES = OFF;
	SOFT_BUFFER_INSERTION = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = OFF;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = PARTIAL;
	CARRY_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000
BEGIN
	REGISTER_OPTIMIZATION = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = OFF;
	MULTI_LEVEL_FACTORING = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = OFF;
	DECOMPOSE_GATES = OFF;
	SOFT_BUFFER_INSERTION = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = ON;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = PARTIAL;
	CARRY_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC
BEGIN
	REGISTER_OPTIMIZATION = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = OFF;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = ON;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = PARTIAL;
	CARRY_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000
BEGIN
	REGISTER_OPTIMIZATION = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = OFF;
	MULTI_LEVEL_FACTORING = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = OFF;
	DECOMPOSE_GATES = OFF;
	SOFT_BUFFER_INSERTION = ON;
	IGNORE_SOFT_BUFFERS = ON;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = OFF;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = PARTIAL;
	CARRY_CHAIN_LENGTH = 32;
	CARRY_CHAIN = MANUAL;
	CASCADE_CHAIN_LENGTH = 2;
	CASCADE_CHAIN = MANUAL;
END;