Using Smartmodels in Modelsim
Preparing SmartModels for use in Modelsim
(Follow instructions on page UM-456 of Modelsim 5.7f User's Manual.)
1.  Edit any/all modelsim.ini files so that the following two lines (in [lmc] section) are uncommented.

libsm = $MODEL_TECH/libsm.dll

libswift = $LMC_HOME/lib/hp700.lib/libswift.sl

2.  Run the following commands in /net/edg/disk6/lmc/modelsim (created this directory first)
sm_entity -all > sml.vhd
vlib lmc
vcom -work lmc sml.vhd

sm_entity -all -c -xe -xa > smlcomp.vhd
Edit the file smlcomp.vhd and add the lines in bold below:

library ieee;
use ieee.std_logic_1164.all;
package sml is
    <component declarations go here>
end sml;

vcom -work lmc smlcomp.vhd

3.  That's it.  You can now use smartmodels by including them in your vhdl file with:

library lmc;
use lmc.sml.all;
Using Modelsim with Design Architect
1.  Create your design with Design Architect, as usual.  Be sure to Check Sheet and Save when finished.

2.  Export VHDL files for your project.  Check-Export VHDL
In the window that appears, enter in the location where you want to files to be created in the "Output to Path" window and be sure to uncheck "Check Only".  You should also be generating Entity and Architecture (the default choice). 

This will create three files in the directory specified in "Output to Path".  If your Design Architect project is named test1, the output files will be:
test1_ent.vhd  --  entity file
test1_structure_arch.vhd  --  architecture file
test1_structure_arch.vxt  --  log of vhdlwrite command

3.  Concatenate the entity and architecture files together to make one file.
cat test1_ent.vhd test1_structure_arch.vhd > test1.vhd

4.  Edit the file test1.vhd.  In the sample file below, italic lines can be deleted and items that changed or were added are in bold.
--------------------------------------------------------
-- VHDL object:   Entity "test1" (component interface "/net/edg/disk2/users/maryh/sdftest/test1:test1")
-- Generated on:  Fri Oct 24 10:09:19 2003
-- Generated by:  User_name_unavailable
-- Source from:   /net/edg/disk2/users/maryh/sdftest/test1/part
-- Program:       VHDLwrite  v8.9_1.8  Thu Sep 20 14:45:33 CAT 2001
--------------------------------------------------------
-- LIBRARY STATEMENT
LIBRARY ieee;
library lmc;
library max;
library work;
-- PACKAGE STATEMENT
USE ieee.std_logic_1164.ALL;
use lmc.sml.all;
use max.max_components.all;
entity test1 is
   -- GENERIC LIST

   -- PORT LIST
   port(
      clock_in : inout std_logic;
      five : inout std_logic;
      four : inout std_logic;
      not_count1 : inout std_logic;
      one : inout std_logic;
      seven : inout std_logic;
      six : inout std_logic;
      three : inout std_logic;
      two : inout std_logic;
      zero : inout std_logic
   );
   attribute original_name : string;

end test1;
--------------------------------------------------------
-- VHDL object:   Architecture "structure" (schematic "$USERS/maryh/sdftest/test1/schematic") of entity "t
est1" (component interface "/net/edg/disk2/users/maryh/sdftest/test1:test1")
-- Generated on:  Fri Oct 24 10:09:19 2003
-- Generated by:  User_name_unavailable
-- Source from:   $USERS/maryh/sdftest/test1/schematic
-- Program:       VHDLwrite  v8.9_1.8  Thu Sep 20 14:45:33 CAT 2001
--------------------------------------------------------
library ieee;
library max;
library work;
use ieee.std_logic_1164.ALL;
use max.max_components.all;
architecture structure of test1 is
   -- TYPE DECLARATIONS
   -- SIGNAL DECLARATIONS
      signal count : std_logic_vector(3 downto 0);
      signal VCC : std_logic := '1';
      signal ground : std_logic := '0';
      alias count1 : std_logic is count(1);
      alias count2 : std_logic is count(2);
      alias count3 : std_logic is count(3);
   -- COMPONENT_DECLARATIONS
      component counter
         port(
            clk_in : in std_logic;
            count : out std_logic_vector(3 downto 0)
         );
      end component;
      component ttl04_POS
         port(
            I1 : in std_logic;
            O1 : out std_logic
         );
      end component;
      component ttl138
         port(
            A : in std_logic;
            B : in std_logic;
            C : in std_logic;
            G1 : in std_logic;
            G2A : in std_logic;
            G2B : in std_logic;
            Y0 : out std_logic;
            Y1 : out std_logic;
            Y2 : out std_logic;
            Y3 : out std_logic;
            Y4 : out std_logic;
            Y5 : out std_logic;
            Y6 : out std_logic;
            Y7 : out std_logic
         );
      end component;
   -- INLINE CONFIGURATIONS
      for I_0361 : ttl138 use entity lmc.ttl138(black_box);   BE SURE TO DELETE THE (BLACK BOX)
      for I_036203 : counter use entity work.counter(structure);
      for I_036419 : ttl04_POS use entity lmc.ttl04_POS(black_box);BE SURE TO DELETE THE _POS & (BLACK BOX)
   begin
      -- CONCURRENT SIGNAL ASSIGNMENTS
         VCC <= '1';
         ground <= '0';
      -- COMPONENT INSTANTIATIONS
         I_0361 : ttl138
            port map(
               A => count1,
               B => count2,
               C => count3,
               G1 => VCC,
               G2A => ground,
               G2B => ground,
               Y0 => zero,
               Y1 => one,
               Y2 => two,
               Y3 => three,
               Y4 => four,
               Y5 => five,
               Y6 => six,
               Y7 => seven
            );
         I_036203 : counter
            port map(
               clk_in => clock_in,
               count(3 downto 0) => count(3 downto 0)
            );
         I_036419 : ttl04_POS
            port map(
               I1 => count1,
               O1 => not_count1
            );
      -- FRAMES
   end structure;
5.  Make sure that you have mapped all the libraries required.  The command vmap should show something like:

[maryh@volt ~/sdftest/vhdl]$ vmap
Reading modelsim.ini
"work" maps to directory /users/maryh/sdftest/vhdl/modelsim_work.
"lmc" maps to directory /net/edg/disk6/lmc/modelsim/lmc.
"max" maps to directory /net/edg/disk6/modeltech/altera/vhdl/max.
Reading /net/model/modeltech/hp700/../modelsim.ini
"std" maps to directory /net/model/modeltech/hp700/../std.
"ieee" maps to directory /net/model/modeltech/hp700/../ieee.
"verilog" maps to directory /net/model/modeltech/hp700/../verilog.
"vital2000" maps to directory /net/model/modeltech/hp700/../vital2000.
"std_developerskit" maps to directory /net/model/modeltech/hp700/../std_developerskit.
"synopsys" maps to directory /net/model/modeltech/hp700/../synopsys.
"modelsim_lib" maps to directory /net/model/modeltech/hp700/../modelsim_lib.
"stratix" maps to directory /net/model/modeltech/hp700/../altera/vhdl/stratix.
"altera_mf" maps to directory /net/model/modeltech/hp700/../altera/vhdl/altera_mf.
If you don't have all the correct mappings, make them with vmap.  For example, the lmc vmap command would be.

vmap lmc /net/edg/disk6/lmc/modelsim/lmc

6.  Compile the file test1.vhd

vcom test1.vhd

7. Start the simulator with vsim.
In the Modelsim window that appears, choose "Simulate", then "Simulate...".  Open the work library and highlight test1.  Then click ok.

8.  Once you get the VSIM> prompt, you can start simulating.  Go View-Signals to see the available signals and View-Wave to show the waveform window.  Assign values to the signals in the Signals window, by highlighting the signal in question and selecting Edit-Force or Edit-Clock.  Then, put the signals from the signal window in the waveform window with Add-Wave-Signals in Region.  Then, go to the waveform file and run the simulation.


Mary Heintz
October 24, 2003