Hierarchy Input Constant Input Unused Input Floating Input Output Constant Output Unused Output Floating Output Bidir Constant Bidir Unused Bidir Input only Bidir Output only Bidir
inst88|lpm_counter_component|auto_generated 1 0 0 0 25 0 0 0 0 0 0 0 0
inst88 1 25 0 25 25 25 25 25 0 0 0 0 0
inst7|lpm_counter_component|auto_generated 1 0 0 0 25 0 0 0 0 0 0 0 0
inst7 1 25 0 25 25 25 25 25 0 0 0 0 0
inst51 2 1 0 1 1 1 1 1 0 0 0 0 0
inst256|lpm_counter_component|auto_generated 1 0 0 0 24 0 0 0 0 0 0 0 0
inst256 1 24 0 24 24 24 24 24 0 0 0 0 0
inst1095|LPM_COUNTER_component|auto_generated 1 0 0 0 32 0 0 0 0 0 0 0 0
inst1095 1 0 0 0 32 0 0 0 0 0 0 0 0
inst241|lpm_counter_component|auto_generated 1 0 0 0 24 0 0 0 0 0 0 0 0
inst241 1 0 0 0 24 0 0 0 0 0 0 0 0
inst150|lpm_counter_component|auto_generated 1 0 0 0 8 0 0 0 0 0 0 0 0
inst150 1 0 0 0 8 0 0 0 0 0 0 0 0
inst149|ALTLVDS_TX_component|auto_generated|coreclk_buf 4 3 0 3 1 3 3 3 0 0 0 0 0
inst149|ALTLVDS_TX_component|auto_generated 9 0 0 0 1 0 0 0 0 0 0 0 0
inst149 9 0 0 0 1 0 0 0 0 0 0 0 0
inst148|lpm_counter_component|auto_generated 1 0 0 0 8 0 0 0 0 0 0 0 0
inst148 1 0 0 0 8 0 0 0 0 0 0 0 0
inst147|ALTLVDS_TX_component|auto_generated|coreclk_buf 4 3 0 3 1 3 3 3 0 0 0 0 0
inst147|ALTLVDS_TX_component|auto_generated 9 0 0 0 1 0 0 0 0 0 0 0 0
inst147 9 0 0 0 1 0 0 0 0 0 0 0 0
inst146|lpm_counter_component|auto_generated 1 0 0 0 8 0 0 0 0 0 0 0 0
inst146 1 0 0 0 8 0 0 0 0 0 0 0 0
inst145|ALTLVDS_TX_component|auto_generated|coreclk_buf 4 3 0 3 1 3 3 3 0 0 0 0 0
inst145|ALTLVDS_TX_component|auto_generated 9 0 0 0 1 0 0 0 0 0 0 0 0
inst145 9 0 0 0 1 0 0 0 0 0 0 0 0
inst144|lpm_counter_component|auto_generated 1 0 0 0 8 0 0 0 0 0 0 0 0
inst144 1 0 0 0 8 0 0 0 0 0 0 0 0
inst143|ALTLVDS_TX_component|auto_generated|coreclk_buf 4 3 0 3 1 3 3 3 0 0 0 0 0
inst143|ALTLVDS_TX_component|auto_generated 9 0 0 0 1 0 0 0 0 0 0 0 0
inst143 9 0 0 0 1 0 0 0 0 0 0 0 0
inst142|lpm_counter_component|auto_generated 1 0 0 0 8 0 0 0 0 0 0 0 0
inst142 1 0 0 0 8 0 0 0 0 0 0 0 0
inst139|ALTLVDS_TX_component|auto_generated|coreclk_buf 4 3 0 3 1 3 3 3 0 0 0 0 0
inst139|ALTLVDS_TX_component|auto_generated 9 0 0 0 1 0 0 0 0 0 0 0 0
inst139 9 0 0 0 1 0 0 0 0 0 0 0 0
inst138|lpm_counter_component|auto_generated 1 0 0 0 8 0 0 0 0 0 0 0 0
inst138 1 0 0 0 8 0 0 0 0 0 0 0 0
inst137|ALTLVDS_TX_component|auto_generated|coreclk_buf 4 3 0 3 1 3 3 3 0 0 0 0 0
inst137|ALTLVDS_TX_component|auto_generated 9 0 0 0 1 0 0 0 0 0 0 0 0
inst137 9 0 0 0 1 0 0 0 0 0 0 0 0
inst132|lpm_counter_component|auto_generated 1 0 0 0 8 0 0 0 0 0 0 0 0
inst132 1 0 0 0 8 0 0 0 0 0 0 0 0
inst131|ALTLVDS_TX_component|auto_generated|coreclk_buf 4 3 0 3 1 3 3 3 0 0 0 0 0
inst131|ALTLVDS_TX_component|auto_generated 9 0 0 0 1 0 0 0 0 0 0 0 0
inst131 9 0 0 0 1 0 0 0 0 0 0 0 0
inst136|lpm_counter_component|auto_generated 1 0 0 0 8 0 0 0 0 0 0 0 0
inst136 1 0 0 0 8 0 0 0 0 0 0 0 0
inst133|ALTLVDS_TX_component|auto_generated|coreclk_buf 4 3 0 3 1 3 3 3 0 0 0 0 0
inst133|ALTLVDS_TX_component|auto_generated 9 0 0 0 1 0 0 0 0 0 0 0 0
inst133 9 0 0 0 1 0 0 0 0 0 0 0 0
inst126|lpm_counter_component|auto_generated 1 0 0 0 8 0 0 0 0 0 0 0 0
inst126 1 0 0 0 8 0 0 0 0 0 0 0 0
inst125|ALTLVDS_TX_component|auto_generated|coreclk_buf 4 3 0 3 1 3 3 3 0 0 0 0 0
inst125|ALTLVDS_TX_component|auto_generated 9 0 0 0 1 0 0 0 0 0 0 0 0
inst125 9 0 0 0 1 0 0 0 0 0 0 0 0
inst130|lpm_counter_component|auto_generated 1 0 0 0 8 0 0 0 0 0 0 0 0
inst130 1 0 0 0 8 0 0 0 0 0 0 0 0
inst129|ALTLVDS_TX_component|auto_generated|coreclk_buf 4 3 0 3 1 3 3 3 0 0 0 0 0
inst129|ALTLVDS_TX_component|auto_generated 9 0 0 0 1 0 0 0 0 0 0 0 0
inst129 9 0 0 0 1 0 0 0 0 0 0 0 0
inst18|lpm_counter_component|auto_generated 1 0 0 0 25 0 0 0 0 0 0 0 0
inst18 1 0 0 0 25 0 0 0 0 0 0 0 0
inst90|lpm_counter_component|auto_generated 1 0 0 0 8 0 0 0 0 0 0 0 0
inst90 1 0 0 0 8 0 0 0 0 0 0 0 0
inst87|ALTLVDS_TX_component|auto_generated|coreclk_buf 4 3 0 3 1 3 3 3 0 0 0 0 0
inst87|ALTLVDS_TX_component|auto_generated 9 0 0 0 1 0 0 0 0 0 0 0 0
inst87 9 0 0 0 1 0 0 0 0 0 0 0 0
inst19|lpm_counter_component|auto_generated 3 0 0 0 24 0 0 0 0 0 0 0 0
inst19 3 0 0 0 24 0 0 0 0 0 0 0 0
inst|lpm_counter_component|auto_generated 1 0 0 0 24 0 0 0 0 0 0 0 0
inst 1 0 0 0 24 0 0 0 0 0 0 0 0
inst45|inst25 2 0 0 0 1 0 0 0 0 0 0 0 0
inst45|inst24 2 0 0 0 1 0 0 0 0 0 0 0 0
inst45|inst23 2 0 0 0 1 0 0 0 0 0 0 0 0
inst45|inst22 2 0 0 0 1 0 0 0 0 0 0 0 0
inst45|inst21 2 0 0 0 1 0 0 0 0 0 0 0 0
inst45|inst20 2 0 0 0 1 0 0 0 0 0 0 0 0
inst45|inst19 2 0 0 0 1 0 0 0 0 0 0 0 0
inst45|inst18 2 0 0 0 1 0 0 0 0 0 0 0 0
inst45|inst17 2 0 0 0 1 0 0 0 0 0 0 0 0
inst45|inst16 2 0 0 0 1 0 0 0 0 0 0 0 0
inst45 2 0 0 0 10 0 0 0 0 0 0 0 0
inst14 2 0 0 0 1 0 0 0 0 0 0 0 0
inst15 2 0 0 0 1 0 0 0 0 0 0 0 0
inst141|ALTLVDS_RX_component|auto_generated|rx_outclock_buf 4 3 0 3 1 3 3 3 0 0 0 0 0
inst141|ALTLVDS_RX_component|auto_generated|lock_cnt_accum40a 7 0 0 0 9 0 0 0 0 0 0 0 0
inst141|ALTLVDS_RX_component|auto_generated 2 0 0 0 10 0 0 0 0 0 0 0 0
inst141 2 2 0 2 10 2 2 2 0 0 0 0 0
inst140|ALTLVDS_RX_component|auto_generated|rx_outclock_buf 4 3 0 3 1 3 3 3 0 0 0 0 0
inst140|ALTLVDS_RX_component|auto_generated|lock_cnt_accum40a 7 0 0 0 9 0 0 0 0 0 0 0 0
inst140|ALTLVDS_RX_component|auto_generated 2 0 0 0 10 0 0 0 0 0 0 0 0
inst140 2 2 0 2 10 2 2 2 0 0 0 0 0
inst116|ADC_VERSION_lpm_constant_369_component 0 32 0 32 32 32 32 32 0 0 0 0 0
inst116 0 0 0 0 32 0 0 0 0 0 0 0 0
inst96|LPM_COUNTER_component|auto_generated 1 0 0 0 32 0 0 0 0 0 0 0 0
inst96 1 0 0 0 32 0 0 0 0 0 0 0 0
inst95|inst1|sfp_reco_inst|basic|a5|bundle 187 42 10 42 221 42 42 42 0 0 0 0 0
inst95|inst1|sfp_reco_inst|basic|a5|pif[1].pif_arb 2 0 0 0 1 0 0 0 0 0 0 0 0
inst95|inst1|sfp_reco_inst|basic|a5|pif[0].pif_arb 2 0 0 0 1 0 0 0 0 0 0 0 0
inst95|inst1|sfp_reco_inst|basic|a5|lif[0].logical_if|pif_tbus_mux 27 0 0 0 8 0 0 0 0 0 0 0 0
inst95|inst1|sfp_reco_inst|basic|a5|lif[0].logical_if|lif_csr|l2paddr 16 0 0 0 12 0 0 0 0 0 0 0 0
inst95|inst1|sfp_reco_inst|basic|a5|lif[0].logical_if|lif_csr|l2pch 8 0 0 0 36 0 0 0 0 0 0 0 0
inst95|inst1|sfp_reco_inst|basic|a5|lif[0].logical_if|lif_csr 57 0 0 0 93 0 0 0 0 0 0 0 0
inst95|inst1|sfp_reco_inst|basic|a5|lif[0].logical_if 122 0 0 0 151 0 0 0 0 0 0 0 0
inst95|inst1|sfp_reco_inst|basic|a5 135 0 0 0 207 0 0 0 0 0 0 0 0
inst95|inst1|sfp_reco_inst|basic 135 0 0 0 207 0 0 0 0 0 0 0 0
inst95|inst1|sfp_reco_inst|cal_seq 13 14 0 14 14 14 14 14 0 0 0 0 0
inst95|inst1|sfp_reco_inst|direct.sc_direct|mutex_inst 74 1 2 1 72 1 1 1 0 0 0 0 0
inst95|inst1|sfp_reco_inst|direct.sc_direct 73 0 0 0 71 0 0 0 0 0 0 0 0
inst95|inst1|sfp_reco_inst|offset.sc_offset|offset_cancellation_av|mutex_inst 74 17 2 17 72 17 17 17 0 0 0 0 0
inst95|inst1|sfp_reco_inst|offset.sc_offset|offset_cancellation_av|wait_gen|rst_sync 3 1 0 1 1 1 1 1 0 0 0 0 0
inst95|inst1|sfp_reco_inst|offset.sc_offset|offset_cancellation_av|wait_gen 3 0 0 0 1 0 0 0 0 0 0 0 0
inst95|inst1|sfp_reco_inst|offset.sc_offset|offset_cancellation_av 82 0 32 0 72 0 0 0 0 0 0 0 0
inst95|inst1|sfp_reco_inst|offset.sc_offset 105 24 0 24 72 24 24 24 0 0 0 0 0
inst95|inst1|sfp_reco_inst|arbiter 11 0 0 0 10 0 0 0 0 0 0 0 0
inst95|inst1|sfp_reco_inst|inst_reconfig_reset_sync 3 1 0 1 1 1 1 1 0 0 0 0 0
inst95|inst1|sfp_reco_inst 153 53 0 53 209 53 53 53 0 0 0 0 0
inst95|inst1 135 2 0 2 174 2 2 2 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|gen_embedded_reset.reset_controller|g_rx.g_rx[0].g_rx.counter_rx_ready 4 1 0 1 1 1 1 1 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|gen_embedded_reset.reset_controller|g_rx.g_rx[0].g_rx.counter_rx_digitalreset 4 0 0 0 2 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|gen_embedded_reset.reset_controller|g_rx.g_rx[0].g_rx.counter_rx_analogreset 4 1 0 1 2 1 1 1 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|gen_embedded_reset.reset_controller|g_rx.g_rx[0].g_rx.resync_rx_cal_busy 5 0 0 0 3 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|gen_embedded_reset.reset_controller|g_tx.g_tx[0].g_tx.counter_tx_ready 4 1 0 1 1 1 1 1 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|gen_embedded_reset.reset_controller|g_tx.g_tx[0].g_tx.counter_tx_digitalreset 4 0 0 0 2 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|gen_embedded_reset.reset_controller|g_tx.g_tx[0].g_tx.resync_tx_cal_busy 5 0 0 0 3 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|gen_embedded_reset.reset_controller|g_pll.counter_pll_powerdown 4 2 0 2 2 2 2 2 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|gen_embedded_reset.reset_controller 11 2 0 2 6 2 2 2 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|csr_pcs|mux_rlv|o_narrow 6 0 0 0 1 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|csr_pcs|mux_rlv 7 0 0 0 1 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|csr_pcs|mux_tx_phase_comp_fifo_error|o_narrow 6 0 0 0 1 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|csr_pcs|mux_tx_phase_comp_fifo_error 7 0 0 0 1 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|csr_pcs|mux_rx_bitslipboundaryselectout|o_narrow 10 0 0 0 5 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|csr_pcs|mux_rx_bitslipboundaryselectout 11 0 0 0 5 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|csr_pcs|mux_rx_phase_comp_fifo_error|o_narrow 6 0 0 0 1 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|csr_pcs|mux_rx_phase_comp_fifo_error 7 0 0 0 1 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|csr_pcs|mux_rx_a1a2sizeout|o_narrow 9 0 0 0 4 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|csr_pcs|mux_rx_a1a2sizeout 10 0 0 0 4 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|csr_pcs|mux_rx_disperr|o_narrow 9 0 0 0 4 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|csr_pcs|mux_rx_disperr 10 0 0 0 4 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|csr_pcs|mux_rx_errdetect|o_narrow 9 0 0 0 4 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|csr_pcs|mux_rx_errdetect 10 0 0 0 4 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|csr_pcs|mux_rx_syncstatus|o_narrow 9 0 0 0 4 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|csr_pcs|mux_rx_syncstatus 10 0 0 0 4 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|csr_pcs|mux_rx_patterndetect|o_narrow 9 0 0 0 4 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|csr_pcs|mux_rx_patterndetect 10 0 0 0 4 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|csr_pcs|wmux_rx_a1a2size|o_narrow 6 0 0 0 1 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|csr_pcs|wmux_rx_a1a2size 7 0 0 0 2 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|csr_pcs|wmux_rx_bitslip|o_narrow 6 0 0 0 1 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|csr_pcs|wmux_rx_bitslip 7 0 0 0 2 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|csr_pcs|wmux_rx_bytereversalenable|o_narrow 6 0 0 0 1 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|csr_pcs|wmux_rx_bytereversalenable 7 0 0 0 2 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|csr_pcs|wmux_rx_bitreversalenable|o_narrow 6 0 0 0 1 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|csr_pcs|wmux_rx_bitreversalenable 7 0 0 0 2 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|csr_pcs|wmux_rx_enapatternalign|o_narrow 6 0 0 0 1 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|csr_pcs|wmux_rx_enapatternalign 7 0 0 0 2 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|csr_pcs|wmux_rx_invpolarity|o_narrow 6 0 0 0 1 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|csr_pcs|wmux_rx_invpolarity 7 0 0 0 2 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|csr_pcs|wmux_tx_bitslipboundaryselect|o_narrow 10 0 0 0 5 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|csr_pcs|wmux_tx_bitslipboundaryselect 15 0 0 0 10 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|csr_pcs|wmux_tx_invpolarity|o_narrow 6 0 0 0 1 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|csr_pcs|wmux_tx_invpolarity 7 0 0 0 2 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|csr_pcs 74 0 27 0 43 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|top_wait|rst_sync 3 1 0 1 1 1 1 1 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|top_wait 3 0 0 0 1 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|csr 54 0 29 0 42 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|transceiver_core|av_xcvr_data_adapter_inst 108 0 0 0 112 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|transceiver_core|av_reconfig_bundle_merger_inst 232 0 4 0 232 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_xcvr_avmm|avmm_interface_insts[0].sv_xcvr_avmm_csr_inst|gen_status_reg_rx.alt_xcvr_resync_inst 3 0 0 0 1 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_xcvr_avmm|avmm_interface_insts[0].sv_xcvr_avmm_csr_inst|gen_status_reg_tx.alt_xcvr_resync_inst 3 0 0 0 1 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_xcvr_avmm|avmm_interface_insts[0].sv_xcvr_avmm_csr_inst 30 2 11 2 23 2 2 2 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_xcvr_avmm|avmm_interface_insts[0].av_reconfig_bundle_to_xcvr_inst 111 5 22 5 94 5 5 5 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_xcvr_avmm 415 2 65 2 88 2 2 2 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_tx_pld_pcs_interface 217 0 0 0 99 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_common_pld_pcs_interface 146 0 0 0 119 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs 167 0 0 0 145 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_rx_pcs_pma_interface 125 60 0 60 48 60 60 60 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_tx_pcs_pma_interface 56 0 0 0 100 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs 230 3 0 3 278 3 3 3 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_common_pcs_pma_interface 194 20 0 20 183 20 20 20 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_rx_pld_pcs_interface 156 0 0 0 266 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch[0].inst_av_pcs_ch 461 49 0 49 601 49 49 49 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs 429 0 0 0 569 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst 132 66 9 66 64 66 66 66 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pma|av_tx_pma 72 1 6 1 58 1 1 1 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pma|av_rx_pma 47 0 0 0 95 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pma 80 1 1 1 153 1 1 1 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst 164 16 0 16 132 16 16 16 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_tx_plls.gen_tx_plls.tx_plls|pll[0].avmm.av_xcvr_avmm_csr_inst|gen_status_reg_pll.alt_xcvr_resync_inst 3 0 0 0 1 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_tx_plls.gen_tx_plls.tx_plls|pll[0].avmm.av_xcvr_avmm_csr_inst 25 0 14 0 16 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_tx_plls.gen_tx_plls.tx_plls|pll[0].avmm.av_reconfig_bundle_to_xcvr_inst 111 6 22 6 92 6 6 6 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_tx_plls.gen_tx_plls.tx_plls 73 7 1 7 55 7 7 7 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5|transceiver_core 212 0 4 0 181 0 0 0 0 0 0 0 0
inst95|inst24|gx1_2gbps_inst|A5 247 0 5 0 208 0 0 0 0 0 0 0 0
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