Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
inst88|lpm_counter_component|auto_generated |
1 |
0 |
0 |
0 |
25 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst88 |
1 |
25 |
0 |
25 |
25 |
25 |
25 |
25 |
0 |
0 |
0 |
0 |
0 |
inst7|lpm_counter_component|auto_generated |
1 |
0 |
0 |
0 |
25 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst7 |
1 |
25 |
0 |
25 |
25 |
25 |
25 |
25 |
0 |
0 |
0 |
0 |
0 |
inst51 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst256|lpm_counter_component|auto_generated |
1 |
0 |
0 |
0 |
24 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst256 |
1 |
24 |
0 |
24 |
24 |
24 |
24 |
24 |
0 |
0 |
0 |
0 |
0 |
inst1095|LPM_COUNTER_component|auto_generated |
1 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst1095 |
1 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst241|lpm_counter_component|auto_generated |
1 |
0 |
0 |
0 |
24 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst241 |
1 |
0 |
0 |
0 |
24 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst150|lpm_counter_component|auto_generated |
1 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst150 |
1 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst149|ALTLVDS_TX_component|auto_generated|coreclk_buf |
4 |
3 |
0 |
3 |
1 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst149|ALTLVDS_TX_component|auto_generated |
9 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst149 |
9 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst148|lpm_counter_component|auto_generated |
1 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst148 |
1 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst147|ALTLVDS_TX_component|auto_generated|coreclk_buf |
4 |
3 |
0 |
3 |
1 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst147|ALTLVDS_TX_component|auto_generated |
9 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst147 |
9 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst146|lpm_counter_component|auto_generated |
1 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst146 |
1 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst145|ALTLVDS_TX_component|auto_generated|coreclk_buf |
4 |
3 |
0 |
3 |
1 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst145|ALTLVDS_TX_component|auto_generated |
9 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst145 |
9 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst144|lpm_counter_component|auto_generated |
1 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst144 |
1 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst143|ALTLVDS_TX_component|auto_generated|coreclk_buf |
4 |
3 |
0 |
3 |
1 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst143|ALTLVDS_TX_component|auto_generated |
9 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst143 |
9 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst142|lpm_counter_component|auto_generated |
1 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst142 |
1 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst139|ALTLVDS_TX_component|auto_generated|coreclk_buf |
4 |
3 |
0 |
3 |
1 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst139|ALTLVDS_TX_component|auto_generated |
9 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst139 |
9 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst138|lpm_counter_component|auto_generated |
1 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst138 |
1 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst137|ALTLVDS_TX_component|auto_generated|coreclk_buf |
4 |
3 |
0 |
3 |
1 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst137|ALTLVDS_TX_component|auto_generated |
9 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst137 |
9 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst132|lpm_counter_component|auto_generated |
1 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst132 |
1 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst131|ALTLVDS_TX_component|auto_generated|coreclk_buf |
4 |
3 |
0 |
3 |
1 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst131|ALTLVDS_TX_component|auto_generated |
9 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst131 |
9 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst136|lpm_counter_component|auto_generated |
1 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst136 |
1 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst133|ALTLVDS_TX_component|auto_generated|coreclk_buf |
4 |
3 |
0 |
3 |
1 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst133|ALTLVDS_TX_component|auto_generated |
9 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst133 |
9 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst126|lpm_counter_component|auto_generated |
1 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst126 |
1 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst125|ALTLVDS_TX_component|auto_generated|coreclk_buf |
4 |
3 |
0 |
3 |
1 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst125|ALTLVDS_TX_component|auto_generated |
9 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst125 |
9 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst130|lpm_counter_component|auto_generated |
1 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst130 |
1 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst129|ALTLVDS_TX_component|auto_generated|coreclk_buf |
4 |
3 |
0 |
3 |
1 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst129|ALTLVDS_TX_component|auto_generated |
9 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst129 |
9 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst18|lpm_counter_component|auto_generated |
1 |
0 |
0 |
0 |
25 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst18 |
1 |
0 |
0 |
0 |
25 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst90|lpm_counter_component|auto_generated |
1 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst90 |
1 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst87|ALTLVDS_TX_component|auto_generated|coreclk_buf |
4 |
3 |
0 |
3 |
1 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst87|ALTLVDS_TX_component|auto_generated |
9 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst87 |
9 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst19|lpm_counter_component|auto_generated |
3 |
0 |
0 |
0 |
24 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst19 |
3 |
0 |
0 |
0 |
24 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|lpm_counter_component|auto_generated |
1 |
0 |
0 |
0 |
24 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst |
1 |
0 |
0 |
0 |
24 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst45|inst25 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst45|inst24 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst45|inst23 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst45|inst22 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst45|inst21 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst45|inst20 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst45|inst19 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst45|inst18 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst45|inst17 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst45|inst16 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst45 |
2 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst14 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst15 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst141|ALTLVDS_RX_component|auto_generated|rx_outclock_buf |
4 |
3 |
0 |
3 |
1 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst141|ALTLVDS_RX_component|auto_generated|lock_cnt_accum40a |
7 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst141|ALTLVDS_RX_component|auto_generated |
2 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst141 |
2 |
2 |
0 |
2 |
10 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
inst140|ALTLVDS_RX_component|auto_generated|rx_outclock_buf |
4 |
3 |
0 |
3 |
1 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst140|ALTLVDS_RX_component|auto_generated|lock_cnt_accum40a |
7 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst140|ALTLVDS_RX_component|auto_generated |
2 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst140 |
2 |
2 |
0 |
2 |
10 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
inst116|ADC_VERSION_lpm_constant_369_component |
0 |
32 |
0 |
32 |
32 |
32 |
32 |
32 |
0 |
0 |
0 |
0 |
0 |
inst116 |
0 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst96|LPM_COUNTER_component|auto_generated |
1 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst96 |
1 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst95|inst1|sfp_reco_inst|basic|a5|bundle |
187 |
42 |
10 |
42 |
221 |
42 |
42 |
42 |
0 |
0 |
0 |
0 |
0 |
inst95|inst1|sfp_reco_inst|basic|a5|pif[1].pif_arb |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst95|inst1|sfp_reco_inst|basic|a5|pif[0].pif_arb |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst95|inst1|sfp_reco_inst|basic|a5|lif[0].logical_if|pif_tbus_mux |
27 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst95|inst1|sfp_reco_inst|basic|a5|lif[0].logical_if|lif_csr|l2paddr |
16 |
0 |
0 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst95|inst1|sfp_reco_inst|basic|a5|lif[0].logical_if|lif_csr|l2pch |
8 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst95|inst1|sfp_reco_inst|basic|a5|lif[0].logical_if|lif_csr |
57 |
0 |
0 |
0 |
93 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst95|inst1|sfp_reco_inst|basic|a5|lif[0].logical_if |
122 |
0 |
0 |
0 |
151 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst95|inst1|sfp_reco_inst|basic|a5 |
135 |
0 |
0 |
0 |
207 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst95|inst1|sfp_reco_inst|basic |
135 |
0 |
0 |
0 |
207 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst95|inst1|sfp_reco_inst|cal_seq |
13 |
14 |
0 |
14 |
14 |
14 |
14 |
14 |
0 |
0 |
0 |
0 |
0 |
inst95|inst1|sfp_reco_inst|direct.sc_direct|mutex_inst |
74 |
1 |
2 |
1 |
72 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst95|inst1|sfp_reco_inst|direct.sc_direct |
73 |
0 |
0 |
0 |
71 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst95|inst1|sfp_reco_inst|offset.sc_offset|offset_cancellation_av|mutex_inst |
74 |
17 |
2 |
17 |
72 |
17 |
17 |
17 |
0 |
0 |
0 |
0 |
0 |
inst95|inst1|sfp_reco_inst|offset.sc_offset|offset_cancellation_av|wait_gen|rst_sync |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst95|inst1|sfp_reco_inst|offset.sc_offset|offset_cancellation_av|wait_gen |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst95|inst1|sfp_reco_inst|offset.sc_offset|offset_cancellation_av |
82 |
0 |
32 |
0 |
72 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst95|inst1|sfp_reco_inst|offset.sc_offset |
105 |
24 |
0 |
24 |
72 |
24 |
24 |
24 |
0 |
0 |
0 |
0 |
0 |
inst95|inst1|sfp_reco_inst|arbiter |
11 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst95|inst1|sfp_reco_inst|inst_reconfig_reset_sync |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst95|inst1|sfp_reco_inst |
153 |
53 |
0 |
53 |
209 |
53 |
53 |
53 |
0 |
0 |
0 |
0 |
0 |
inst95|inst1 |
135 |
2 |
0 |
2 |
174 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
inst95|inst24|gx1_2gbps_inst|A5|gen_embedded_reset.reset_controller|g_rx.g_rx[0].g_rx.counter_rx_ready |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
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inst93|inst1|sfp_reco_inst|basic|a5|pif[0].pif_arb |
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inst93|inst1|sfp_reco_inst|offset.sc_offset|offset_cancellation_av |
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inst93|inst1|sfp_reco_inst|offset.sc_offset |
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inst93|inst1|sfp_reco_inst|arbiter |
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inst93|inst1|sfp_reco_inst|inst_reconfig_reset_sync |
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inst93|inst1|sfp_reco_inst |
153 |
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209 |
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inst93|inst1 |
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174 |
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inst93|inst24|gx1_2gbps_inst|A5|gen_embedded_reset.reset_controller|g_rx.g_rx[0].g_rx.counter_rx_ready |
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inst93|inst24|gx1_2gbps_inst|A5|gen_embedded_reset.reset_controller|g_rx.g_rx[0].g_rx.counter_rx_digitalreset |
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inst93|inst24|gx1_2gbps_inst|A5|gen_embedded_reset.reset_controller|g_rx.g_rx[0].g_rx.counter_rx_analogreset |
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inst93|inst24|gx1_2gbps_inst|A5|gen_embedded_reset.reset_controller|g_rx.g_rx[0].g_rx.resync_rx_cal_busy |
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inst93|inst24|gx1_2gbps_inst|A5|gen_embedded_reset.reset_controller|g_tx.g_tx[0].g_tx.counter_tx_ready |
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inst93|inst24|gx1_2gbps_inst|A5|gen_embedded_reset.reset_controller|g_tx.g_tx[0].g_tx.counter_tx_digitalreset |
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inst93|inst24|gx1_2gbps_inst|A5|gen_embedded_reset.reset_controller|g_tx.g_tx[0].g_tx.resync_tx_cal_busy |
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inst93|inst24|gx1_2gbps_inst|A5|csr_pcs|wmux_rx_bitreversalenable|o_narrow |
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inst93|inst24|gx1_2gbps_inst|A5|csr_pcs|wmux_rx_bitreversalenable |
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inst93|inst24|gx1_2gbps_inst|A5|csr_pcs|wmux_rx_invpolarity |
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inst93|inst24|gx1_2gbps_inst|A5|csr_pcs|wmux_tx_bitslipboundaryselect |
15 |
0 |
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10 |
0 |
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0 |
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inst93|inst24|gx1_2gbps_inst|A5|csr_pcs|wmux_tx_invpolarity|o_narrow |
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inst93|inst24|gx1_2gbps_inst|A5|csr_pcs|wmux_tx_invpolarity |
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0 |
0 |
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inst93|inst24|gx1_2gbps_inst|A5|csr_pcs |
74 |
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27 |
0 |
43 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
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inst93|inst24|gx1_2gbps_inst|A5|top_wait|rst_sync |
3 |
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0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst93|inst24|gx1_2gbps_inst|A5|top_wait |
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0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst93|inst24|gx1_2gbps_inst|A5|csr |
54 |
0 |
29 |
0 |
42 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst93|inst24|gx1_2gbps_inst|A5|transceiver_core|av_xcvr_data_adapter_inst |
108 |
0 |
0 |
0 |
112 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst93|inst24|gx1_2gbps_inst|A5|transceiver_core|av_reconfig_bundle_merger_inst |
232 |
0 |
4 |
0 |
232 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst93|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_xcvr_avmm|avmm_interface_insts[0].sv_xcvr_avmm_csr_inst|gen_status_reg_rx.alt_xcvr_resync_inst |
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inst93|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_xcvr_avmm|avmm_interface_insts[0].sv_xcvr_avmm_csr_inst|gen_status_reg_tx.alt_xcvr_resync_inst |
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0 |
0 |
0 |
0 |
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0 |
inst93|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_xcvr_avmm|avmm_interface_insts[0].sv_xcvr_avmm_csr_inst |
30 |
2 |
11 |
2 |
23 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
inst93|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_xcvr_avmm|avmm_interface_insts[0].av_reconfig_bundle_to_xcvr_inst |
111 |
5 |
22 |
5 |
94 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
inst93|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_xcvr_avmm |
415 |
2 |
65 |
2 |
88 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
inst93|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_tx_pld_pcs_interface |
217 |
0 |
0 |
0 |
99 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst93|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_common_pld_pcs_interface |
146 |
0 |
0 |
0 |
119 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst93|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs |
167 |
0 |
0 |
0 |
145 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst93|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_rx_pcs_pma_interface |
125 |
60 |
0 |
60 |
48 |
60 |
60 |
60 |
0 |
0 |
0 |
0 |
0 |
inst93|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_tx_pcs_pma_interface |
56 |
0 |
0 |
0 |
100 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst93|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs |
230 |
3 |
0 |
3 |
278 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst93|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_common_pcs_pma_interface |
194 |
20 |
0 |
20 |
183 |
20 |
20 |
20 |
0 |
0 |
0 |
0 |
0 |
inst93|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_rx_pld_pcs_interface |
156 |
0 |
0 |
0 |
266 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst93|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch[0].inst_av_pcs_ch |
461 |
49 |
0 |
49 |
601 |
49 |
49 |
49 |
0 |
0 |
0 |
0 |
0 |
inst93|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs |
429 |
0 |
0 |
0 |
569 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst93|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst |
132 |
66 |
9 |
66 |
64 |
66 |
66 |
66 |
0 |
0 |
0 |
0 |
0 |
inst93|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pma|av_tx_pma |
72 |
1 |
6 |
1 |
58 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst93|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pma|av_rx_pma |
47 |
0 |
0 |
0 |
95 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst93|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pma |
80 |
1 |
1 |
1 |
153 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst93|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst |
164 |
16 |
0 |
16 |
132 |
16 |
16 |
16 |
0 |
0 |
0 |
0 |
0 |
inst93|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_tx_plls.gen_tx_plls.tx_plls|pll[0].avmm.av_xcvr_avmm_csr_inst|gen_status_reg_pll.alt_xcvr_resync_inst |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst93|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_tx_plls.gen_tx_plls.tx_plls|pll[0].avmm.av_xcvr_avmm_csr_inst |
25 |
0 |
14 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst93|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_tx_plls.gen_tx_plls.tx_plls|pll[0].avmm.av_reconfig_bundle_to_xcvr_inst |
111 |
6 |
22 |
6 |
92 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
inst93|inst24|gx1_2gbps_inst|A5|transceiver_core|gen.av_xcvr_native_insts[0].gen_tx_plls.gen_tx_plls.tx_plls |
73 |
7 |
1 |
7 |
55 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
inst93|inst24|gx1_2gbps_inst|A5|transceiver_core |
212 |
0 |
4 |
0 |
181 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst93|inst24|gx1_2gbps_inst|A5 |
247 |
0 |
5 |
0 |
208 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst93|inst24|gx1_2gbps_inst |
248 |
61 |
1 |
61 |
208 |
61 |
61 |
61 |
0 |
0 |
0 |
0 |
0 |
inst93|inst24 |
223 |
8 |
0 |
8 |
172 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
inst93 |
42 |
8 |
0 |
8 |
42 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
inst13|inst1|LPM_COUNTER_component|auto_generated |
3 |
0 |
0 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst13|inst1 |
3 |
0 |
0 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst13|inst |
33 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst13|inst55|altsyncram_component|auto_generated |
61 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst13|inst55 |
61 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst13 |
48 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst86|ALTLVDS_RX_component|auto_generated|rx_outclock_buf |
4 |
3 |
0 |
3 |
1 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst86|ALTLVDS_RX_component|auto_generated|lock_cnt_accum40a |
7 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst86|ALTLVDS_RX_component|auto_generated |
2 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst86 |
2 |
2 |
0 |
2 |
10 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
inst84|ALTLVDS_RX_component|auto_generated|rx_outclock_buf |
4 |
3 |
0 |
3 |
1 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst84|ALTLVDS_RX_component|auto_generated|lock_cnt_accum40a |
7 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst84|ALTLVDS_RX_component|auto_generated |
2 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst84 |
2 |
2 |
0 |
2 |
10 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
inst80|ALTLVDS_RX_component|auto_generated|rx_outclock_buf |
4 |
3 |
0 |
3 |
1 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst80|ALTLVDS_RX_component|auto_generated|lock_cnt_accum40a |
7 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst80|ALTLVDS_RX_component|auto_generated |
2 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst80 |
2 |
2 |
0 |
2 |
10 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
inst79|ALTLVDS_RX_component|auto_generated|rx_outclock_buf |
4 |
3 |
0 |
3 |
1 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst79|ALTLVDS_RX_component|auto_generated|lock_cnt_accum40a |
7 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst79|ALTLVDS_RX_component|auto_generated |
2 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst79 |
2 |
2 |
0 |
2 |
10 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
inst78|ALTLVDS_RX_component|auto_generated|rx_outclock_buf |
4 |
3 |
0 |
3 |
1 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst78|ALTLVDS_RX_component|auto_generated|lock_cnt_accum40a |
7 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst78|ALTLVDS_RX_component|auto_generated |
2 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst78 |
2 |
2 |
0 |
2 |
10 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
inst77|ALTLVDS_RX_component|auto_generated|rx_outclock_buf |
4 |
3 |
0 |
3 |
1 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst77|ALTLVDS_RX_component|auto_generated|lock_cnt_accum40a |
7 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst77|ALTLVDS_RX_component|auto_generated |
2 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst77 |
2 |
2 |
0 |
2 |
10 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
inst29|ALTLVDS_RX_component|auto_generated|rx_outclock_buf |
4 |
3 |
0 |
3 |
1 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst29|ALTLVDS_RX_component|auto_generated|lock_cnt_accum40a |
7 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst29|ALTLVDS_RX_component|auto_generated |
2 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst29 |
2 |
2 |
0 |
2 |
10 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
inst28|ALTLVDS_RX_component|auto_generated|rx_outclock_buf |
4 |
3 |
0 |
3 |
1 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst28|ALTLVDS_RX_component|auto_generated|lock_cnt_accum40a |
7 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst28|ALTLVDS_RX_component|auto_generated |
2 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst28 |
2 |
2 |
0 |
2 |
10 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
inst27|ALTLVDS_RX_component|auto_generated|rx_outclock_buf |
4 |
3 |
0 |
3 |
1 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst27|ALTLVDS_RX_component|auto_generated|lock_cnt_accum40a |
7 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst27|ALTLVDS_RX_component|auto_generated |
2 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst27 |
2 |
2 |
0 |
2 |
10 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
inst26|ALTLVDS_RX_component|auto_generated|rx_outclock_buf |
4 |
3 |
0 |
3 |
1 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst26|ALTLVDS_RX_component|auto_generated|lock_cnt_accum40a |
7 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst26|ALTLVDS_RX_component|auto_generated |
2 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst26 |
2 |
2 |
0 |
2 |
10 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
inst24|ALTLVDS_RX_component|auto_generated|rx_outclock_buf |
4 |
3 |
0 |
3 |
1 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst24|ALTLVDS_RX_component|auto_generated|lock_cnt_accum40a |
7 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst24|ALTLVDS_RX_component|auto_generated |
2 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst24 |
2 |
2 |
0 |
2 |
10 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
inst20|ALTLVDS_RX_component|auto_generated|rx_outclock_buf |
4 |
3 |
0 |
3 |
1 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst20|ALTLVDS_RX_component|auto_generated|lock_cnt_accum40a |
7 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst20|ALTLVDS_RX_component|auto_generated |
2 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst20 |
2 |
2 |
0 |
2 |
10 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
inst57 |
926 |
322 |
2 |
322 |
270 |
322 |
322 |
322 |
32 |
0 |
0 |
0 |
0 |
inst81|inst7 |
33 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst8 |
33 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst3 |
33 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst5 |
33 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst1 |
33 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst2 |
33 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst22 |
33 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst23 |
33 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst19 |
33 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst20 |
33 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst16 |
33 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst17 |
33 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst13 |
33 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst14 |
33 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst10 |
33 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst11 |
33 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst61 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst62 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst58 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst59 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst55 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst56 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst52 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst53 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst49 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst50 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst46 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst47 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst43 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst44 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst40 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst41 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst37 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst38 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst34 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst35 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst31 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst32 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst28 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst29 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst25 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81|inst26 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst81 |
271 |
234 |
1 |
234 |
269 |
234 |
234 |
234 |
0 |
0 |
0 |
0 |
0 |
inst134|pll_new_inst |
4 |
1 |
0 |
1 |
8 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst134 |
4 |
4 |
0 |
4 |
7 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
inst16 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst17 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|address_cnt|auto_generated |
9 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2|comp|auto_generated |
20 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst2 |
54 |
1 |
1 |
1 |
33 |
1 |
1 |
1 |
2 |
0 |
0 |
0 |
2 |