Trace Analysis

Performed signal integrity tests for some BLVDS nets on the QEB_ Backplane, using the Interconnect Synthesis tool by Mentor Graphics.
The IBIS models for the DS92001 B/LVDS-BLVDS Buffers were vendor supplied. The termination resistors are 50 Ohm.
Each card is considered to add a load to the bus, mostly a bulk capacitance, resulting from the connector and PCB trace (each 2-3 pF/line) and input buffer (4-5 pF/line) for a total of about 10pF/line.

The following plots show examples:

    Plot of signal on line A3 with no cards installed:

    Plot of signal on line A3 with 3 cards installed in slots 9, 20 and 21:

    Plot of signal on A3 line with 13 cards installed in slots 9,...,21 (notice grater dealy to slot 21 that with just 3 cards installed):

    Plot of signal on SCLK line with 2 cards installed in slots 20, 21:

For questions regarding this page contact Mircea Bogdan.
Revised: August, 2005