Hierarchy Input Constant Input Unused Input Floating Input Output Constant Output Unused Output Floating Output Bidir Constant Bidir Unused Bidir Input only Bidir Output only Bidir
inst7|lpm_counter_component|auto_generated 1 0 0 0 25 0 0 0 0 0 0 0 0
inst7 1 25 0 25 25 25 25 25 0 0 0 0 0
inst19|lpm_counter_component|auto_generated 3 0 0 0 24 0 0 0 0 0 0 0 0
inst19 3 0 0 0 24 0 0 0 0 0 0 0 0
inst18|lpm_counter_component|auto_generated 1 0 0 0 25 0 0 0 0 0 0 0 0
inst18 1 25 0 25 25 25 25 25 0 0 0 0 0
inst21 1 1 0 1 2 1 1 1 0 0 0 0 0
inst9 2 0 0 0 1 0 0 0 0 0 0 0 0
inst5 1 1 0 1 2 1 1 1 0 0 0 0 0
inst1 2 0 0 0 1 0 0 0 0 0 0 0 0
inst129|lpm_counter_component|auto_generated 1 0 0 0 16 0 0 0 0 0 0 0 0
inst129 1 0 0 0 16 0 0 0 0 0 0 0 0
inst125 17 0 0 0 16 0 0 0 0 0 0 0 0
inst48 2 0 0 0 1 0 0 0 0 0 0 0 0
inst84 2 0 0 0 1 0 0 0 0 0 0 0 0
inst87 2 0 0 0 1 0 0 0 0 0 0 0 0
inst89 2 0 0 0 1 0 0 0 0 0 0 0 0
inst90 2 0 0 0 1 0 0 0 0 0 0 0 0
inst91 2 0 0 0 1 0 0 0 0 0 0 0 0
inst103 2 0 0 0 1 0 0 0 0 0 0 0 0
inst197|lpm_mux_component|auto_generated 11 0 0 0 1 0 0 0 0 0 0 0 0
inst197 11 0 0 0 1 0 0 0 0 0 0 0 0
inst194 2 0 0 0 1 0 0 0 0 0 0 0 0
inst127|lpm_counter_component|auto_generated 1 0 0 0 16 0 0 0 0 0 0 0 0
inst127 1 0 0 0 16 0 0 0 0 0 0 0 0
inst105 17 0 0 0 16 0 0 0 0 0 0 0 0
inst67 2 0 0 0 1 0 0 0 0 0 0 0 0
inst137 2 0 0 0 1 0 0 0 0 0 0 0 0
inst153 2 0 0 0 1 0 0 0 0 0 0 0 0
inst154 2 0 0 0 1 0 0 0 0 0 0 0 0
inst166 2 0 0 0 1 0 0 0 0 0 0 0 0
inst167 2 0 0 0 1 0 0 0 0 0 0 0 0
inst180 2 0 0 0 1 0 0 0 0 0 0 0 0
inst198|lpm_mux_component|auto_generated 11 0 0 0 1 0 0 0 0 0 0 0 0
inst198 11 0 0 0 1 0 0 0 0 0 0 0 0
inst193 2 0 0 0 1 0 0 0 0 0 0 0 0
inst100|lpm_counter_component|auto_generated 1 0 0 0 16 0 0 0 0 0 0 0 0
inst100 1 0 0 0 16 0 0 0 0 0 0 0 0
inst97 17 0 0 0 16 0 0 0 0 0 0 0 0
inst74|lpm_counter_component|auto_generated 1 0 0 0 16 0 0 0 0 0 0 0 0
inst74 1 0 0 0 16 0 0 0 0 0 0 0 0
inst42 17 0 0 0 16 0 0 0 0 0 0 0 0
inst|lpm_counter_component|auto_generated 1 0 0 0 24 0 0 0 0 0 0 0 0
inst 1 0 0 0 24 0 0 0 0 0 0 0 0
inst178|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst178|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst178|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst178|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst178|dcfifo_component|auto_generated|wrfull_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst178|dcfifo_component|auto_generated|wrfull_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst178|dcfifo_component|auto_generated|wrfull_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst178|dcfifo_component|auto_generated|wrfull_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst178|dcfifo_component|auto_generated|rdempty_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst178|dcfifo_component|auto_generated|rdempty_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst178|dcfifo_component|auto_generated|rdempty_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst178|dcfifo_component|auto_generated|rdempty_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst178|dcfifo_component|auto_generated|ws_dgrp|dffpipe9 6 0 0 0 5 0 0 0 0 0 0 0 0
inst178|dcfifo_component|auto_generated|ws_dgrp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst178|dcfifo_component|auto_generated|rs_dgwp|dffpipe9 6 0 0 0 5 0 0 0 0 0 0 0 0
inst178|dcfifo_component|auto_generated|rs_dgwp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst178|dcfifo_component|auto_generated|rdaclr 2 1 0 1 1 1 1 1 0 0 0 0 0
inst178|dcfifo_component|auto_generated|fifo_ram 29 0 0 0 16 0 0 0 0 0 0 0 0
inst178|dcfifo_component|auto_generated|wrptr_gp 2 0 0 0 5 0 0 0 0 0 0 0 0
inst178|dcfifo_component|auto_generated|wrptr_g1p 2 0 0 0 5 0 0 0 0 0 0 0 0
inst178|dcfifo_component|auto_generated|rdptr_g1p 3 0 0 0 5 0 0 0 0 0 0 0 0
inst178|dcfifo_component|auto_generated 20 0 0 0 16 0 0 0 0 0 0 0 0
inst178 20 2 0 2 16 2 2 2 0 0 0 0 0
inst177|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst177|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst177|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst177|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst177|dcfifo_component|auto_generated|wrfull_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst177|dcfifo_component|auto_generated|wrfull_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst177|dcfifo_component|auto_generated|wrfull_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst177|dcfifo_component|auto_generated|wrfull_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst177|dcfifo_component|auto_generated|rdempty_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst177|dcfifo_component|auto_generated|rdempty_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst177|dcfifo_component|auto_generated|rdempty_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst177|dcfifo_component|auto_generated|rdempty_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst177|dcfifo_component|auto_generated|ws_dgrp|dffpipe9 6 0 0 0 5 0 0 0 0 0 0 0 0
inst177|dcfifo_component|auto_generated|ws_dgrp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst177|dcfifo_component|auto_generated|rs_dgwp|dffpipe9 6 0 0 0 5 0 0 0 0 0 0 0 0
inst177|dcfifo_component|auto_generated|rs_dgwp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst177|dcfifo_component|auto_generated|rdaclr 2 1 0 1 1 1 1 1 0 0 0 0 0
inst177|dcfifo_component|auto_generated|fifo_ram 29 0 0 0 16 0 0 0 0 0 0 0 0
inst177|dcfifo_component|auto_generated|wrptr_gp 2 0 0 0 5 0 0 0 0 0 0 0 0
inst177|dcfifo_component|auto_generated|wrptr_g1p 2 0 0 0 5 0 0 0 0 0 0 0 0
inst177|dcfifo_component|auto_generated|rdptr_g1p 3 0 0 0 5 0 0 0 0 0 0 0 0
inst177|dcfifo_component|auto_generated 20 0 0 0 16 0 0 0 0 0 0 0 0
inst177 20 2 0 2 16 2 2 2 0 0 0 0 0
inst98|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated|wrfull_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated|wrfull_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated|wrfull_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated|wrfull_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated|rdempty_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated|rdempty_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated|rdempty_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated|rdempty_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated|ws_dgrp|dffpipe9 6 0 0 0 5 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated|ws_dgrp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated|rs_dgwp|dffpipe9 6 0 0 0 5 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated|rs_dgwp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated|rdaclr 2 1 0 1 1 1 1 1 0 0 0 0 0
inst98|dcfifo_component|auto_generated|fifo_ram 29 0 0 0 16 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated|wrptr_gp 2 0 0 0 5 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated|wrptr_g1p 2 0 0 0 5 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated|rdptr_g1p 3 0 0 0 5 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated 20 0 0 0 16 0 0 0 0 0 0 0 0
inst98 20 2 0 2 16 2 2 2 0 0 0 0 0
inst10|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst10|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst10|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst10|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst10|dcfifo_component|auto_generated|wrfull_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst10|dcfifo_component|auto_generated|wrfull_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst10|dcfifo_component|auto_generated|wrfull_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst10|dcfifo_component|auto_generated|wrfull_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst10|dcfifo_component|auto_generated|rdempty_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst10|dcfifo_component|auto_generated|rdempty_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst10|dcfifo_component|auto_generated|rdempty_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst10|dcfifo_component|auto_generated|rdempty_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst10|dcfifo_component|auto_generated|ws_dgrp|dffpipe9 6 0 0 0 5 0 0 0 0 0 0 0 0
inst10|dcfifo_component|auto_generated|ws_dgrp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst10|dcfifo_component|auto_generated|rs_dgwp|dffpipe9 6 0 0 0 5 0 0 0 0 0 0 0 0
inst10|dcfifo_component|auto_generated|rs_dgwp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst10|dcfifo_component|auto_generated|rdaclr 2 1 0 1 1 1 1 1 0 0 0 0 0
inst10|dcfifo_component|auto_generated|fifo_ram 29 0 0 0 16 0 0 0 0 0 0 0 0
inst10|dcfifo_component|auto_generated|wrptr_gp 2 0 0 0 5 0 0 0 0 0 0 0 0
inst10|dcfifo_component|auto_generated|wrptr_g1p 2 0 0 0 5 0 0 0 0 0 0 0 0
inst10|dcfifo_component|auto_generated|rdptr_g1p 3 0 0 0 5 0 0 0 0 0 0 0 0
inst10|dcfifo_component|auto_generated 20 0 0 0 16 0 0 0 0 0 0 0 0
inst10 20 2 0 2 16 2 2 2 0 0 0 0 0
inst116|inst31 14 0 0 0 13 0 0 0 0 0 0 0 0
inst116|inst3|lpm_counter_component|auto_generated 3 0 0 0 13 0 0 0 0 0 0 0 0
inst116|inst3 3 1 0 1 13 1 1 1 0 0 0 0 0
inst116|inst33|lpm_mux_component|auto_generated 28 0 0 0 13 0 0 0 0 0 0 0 0
inst116|inst33 28 0 0 0 13 0 0 0 0 0 0 0 0
inst116|inst32 14 0 0 0 13 0 0 0 0 0 0 0 0
inst116|inst86|altsyncram_component|auto_generated 287 0 0 0 256 0 0 0 0 0 0 0 0
inst116|inst86 287 0 0 0 256 0 0 0 0 0 0 0 0
inst116|inst19|lpm_counter_component|auto_generated 3 0 0 0 24 0 0 0 0 0 0 0 0
inst116|inst19 3 0 0 0 24 0 0 0 0 0 0 0 0
inst116|inst17 2 0 0 0 1 0 0 0 0 0 0 0 0
inst116|inst29 33 0 0 0 32 0 0 0 0 0 0 0 0
inst116|inst30 33 0 0 0 32 0 0 0 0 0 0 0 0
inst116|inst21|lpm_compare_component|auto_generated 34 0 0 0 1 0 0 0 0 0 0 0 0
inst116|inst21 34 0 0 0 1 0 0 0 0 0 0 0 0
inst116|inst27 33 0 0 0 32 0 0 0 0 0 0 0 0
inst116|inst|lpm_counter_component|auto_generated 3 0 0 0 8 0 0 0 0 0 0 0 0
inst116|inst 3 0 0 0 8 0 0 0 0 0 0 0 0
inst116|inst1|lpm_compare_component|auto_generated 17 0 0 0 1 0 0 0 0 0 0 0 0
inst116|inst1 17 0 0 0 1 0 0 0 0 0 0 0 0
inst116|inst2|lpm_counter_component|auto_generated 3 0 0 0 13 0 0 0 0 0 0 0 0
inst116|inst2 3 0 0 0 13 0 0 0 0 0 0 0 0
inst116|inst10|lpm_compare_component|auto_generated 27 0 0 0 1 0 0 0 0 0 0 0 0
inst116|inst10 27 0 0 0 1 0 0 0 0 0 0 0 0
inst116|inst4 2 0 0 0 1 0 0 0 0 0 0 0 0
inst116 371 18 0 18 273 18 18 18 0 0 0 0 0
inst4|inst4 0 0 0 0 16 0 0 0 0 0 0 0 0
inst4|inst25|lpm_add_sub_component|auto_generated 32 0 0 0 16 0 0 0 0 0 0 0 0
inst4|inst25 32 0 0 0 16 0 0 0 0 0 0 0 0
inst4|inst27 17 0 0 0 16 0 0 0 0 0 0 0 0
inst4|inst5|lpm_mux_component|auto_generated 131 0 0 0 65 0 0 0 0 0 0 0 0
inst4|inst5 131 65 0 65 65 65 65 65 0 0 0 0 0
inst4|inst14 66 0 0 0 65 0 0 0 0 0 0 0 0
inst4|inst3|inst253 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst252 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst247|inst 4 1 0 1 4 1 1 1 0 0 0 0 0
inst4|inst3|inst247|inst5 3 0 0 0 2 0 0 0 0 0 0 0 0
inst4|inst3|inst247 5 0 0 0 2 0 0 0 0 0 0 0 0
inst4|inst3|inst232 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst231 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst246|inst 4 1 0 1 4 1 1 1 0 0 0 0 0
inst4|inst3|inst246|inst5 3 0 0 0 2 0 0 0 0 0 0 0 0
inst4|inst3|inst246 5 0 0 0 2 0 0 0 0 0 0 0 0
inst4|inst3|inst248|inst|lpm_add_sub_component|auto_generated 4 0 0 0 3 0 0 0 0 0 0 0 0
inst4|inst3|inst248|inst 4 0 0 0 3 0 0 0 0 0 0 0 0
inst4|inst3|inst248|inst15 4 0 0 0 3 0 0 0 0 0 0 0 0
inst4|inst3|inst248 5 0 0 0 3 0 0 0 0 0 0 0 0
inst4|inst3|inst230 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst228 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst244|inst 4 1 0 1 4 1 1 1 0 0 0 0 0
inst4|inst3|inst244|inst5 3 0 0 0 2 0 0 0 0 0 0 0 0
inst4|inst3|inst244 5 0 0 0 2 0 0 0 0 0 0 0 0
inst4|inst3|inst227 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst226 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst243|inst 4 1 0 1 4 1 1 1 0 0 0 0 0
inst4|inst3|inst243|inst5 3 0 0 0 2 0 0 0 0 0 0 0 0
inst4|inst3|inst243 5 0 0 0 2 0 0 0 0 0 0 0 0
inst4|inst3|inst245|inst|lpm_add_sub_component|auto_generated 4 0 0 0 3 0 0 0 0 0 0 0 0
inst4|inst3|inst245|inst 4 0 0 0 3 0 0 0 0 0 0 0 0
inst4|inst3|inst245|inst15 4 0 0 0 3 0 0 0 0 0 0 0 0
inst4|inst3|inst245 5 0 0 0 3 0 0 0 0 0 0 0 0
inst4|inst3|inst249|inst2|lpm_add_sub_component|auto_generated 6 0 0 0 4 0 0 0 0 0 0 0 0
inst4|inst3|inst249|inst2 6 0 0 0 4 0 0 0 0 0 0 0 0
inst4|inst3|inst249|inst 5 0 0 0 4 0 0 0 0 0 0 0 0
inst4|inst3|inst249 7 0 0 0 4 0 0 0 0 0 0 0 0
inst4|inst3|inst225 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst223 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst240|inst 4 1 0 1 4 1 1 1 0 0 0 0 0
inst4|inst3|inst240|inst5 3 0 0 0 2 0 0 0 0 0 0 0 0
inst4|inst3|inst240 5 0 0 0 2 0 0 0 0 0 0 0 0
inst4|inst3|inst221 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst220 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst239|inst 4 1 0 1 4 1 1 1 0 0 0 0 0
inst4|inst3|inst239|inst5 3 0 0 0 2 0 0 0 0 0 0 0 0
inst4|inst3|inst239 5 0 0 0 2 0 0 0 0 0 0 0 0
inst4|inst3|inst241|inst|lpm_add_sub_component|auto_generated 4 0 0 0 3 0 0 0 0 0 0 0 0
inst4|inst3|inst241|inst 4 0 0 0 3 0 0 0 0 0 0 0 0
inst4|inst3|inst241|inst15 4 0 0 0 3 0 0 0 0 0 0 0 0
inst4|inst3|inst241 5 0 0 0 3 0 0 0 0 0 0 0 0
inst4|inst3|inst219 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst217 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst237|inst 4 1 0 1 4 1 1 1 0 0 0 0 0
inst4|inst3|inst237|inst5 3 0 0 0 2 0 0 0 0 0 0 0 0
inst4|inst3|inst237 5 0 0 0 2 0 0 0 0 0 0 0 0
inst4|inst3|inst216 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst215 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst236|inst 4 1 0 1 4 1 1 1 0 0 0 0 0
inst4|inst3|inst236|inst5 3 0 0 0 2 0 0 0 0 0 0 0 0
inst4|inst3|inst236 5 0 0 0 2 0 0 0 0 0 0 0 0
inst4|inst3|inst238|inst|lpm_add_sub_component|auto_generated 4 0 0 0 3 0 0 0 0 0 0 0 0
inst4|inst3|inst238|inst 4 0 0 0 3 0 0 0 0 0 0 0 0
inst4|inst3|inst238|inst15 4 0 0 0 3 0 0 0 0 0 0 0 0
inst4|inst3|inst238 5 0 0 0 3 0 0 0 0 0 0 0 0
inst4|inst3|inst242|inst2|lpm_add_sub_component|auto_generated 6 0 0 0 4 0 0 0 0 0 0 0 0
inst4|inst3|inst242|inst2 6 0 0 0 4 0 0 0 0 0 0 0 0
inst4|inst3|inst242|inst 5 0 0 0 4 0 0 0 0 0 0 0 0
inst4|inst3|inst242 7 0 0 0 4 0 0 0 0 0 0 0 0
inst4|inst3|inst250|inst3|lpm_add_sub_component|auto_generated 8 0 0 0 5 0 0 0 0 0 0 0 0
inst4|inst3|inst250|inst3 8 0 0 0 5 0 0 0 0 0 0 0 0
inst4|inst3|inst250|inst4 6 0 0 0 5 0 0 0 0 0 0 0 0
inst4|inst3|inst250 9 0 0 0 5 0 0 0 0 0 0 0 0
inst4|inst3|inst214 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst212 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst229|inst 4 1 0 1 4 1 1 1 0 0 0 0 0
inst4|inst3|inst229|inst5 3 0 0 0 2 0 0 0 0 0 0 0 0
inst4|inst3|inst229 5 0 0 0 2 0 0 0 0 0 0 0 0
inst4|inst3|inst209 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst208 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst224|inst 4 1 0 1 4 1 1 1 0 0 0 0 0
inst4|inst3|inst224|inst5 3 0 0 0 2 0 0 0 0 0 0 0 0
inst4|inst3|inst224 5 0 0 0 2 0 0 0 0 0 0 0 0
inst4|inst3|inst233|inst|lpm_add_sub_component|auto_generated 4 0 0 0 3 0 0 0 0 0 0 0 0
inst4|inst3|inst233|inst 4 0 0 0 3 0 0 0 0 0 0 0 0
inst4|inst3|inst233|inst15 4 0 0 0 3 0 0 0 0 0 0 0 0
inst4|inst3|inst233 5 0 0 0 3 0 0 0 0 0 0 0 0
inst4|inst3|inst207 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst205 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst218|inst 4 1 0 1 4 1 1 1 0 0 0 0 0
inst4|inst3|inst218|inst5 3 0 0 0 2 0 0 0 0 0 0 0 0
inst4|inst3|inst218 5 0 0 0 2 0 0 0 0 0 0 0 0
inst4|inst3|inst204 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst203 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst213|inst 4 1 0 1 4 1 1 1 0 0 0 0 0
inst4|inst3|inst213|inst5 3 0 0 0 2 0 0 0 0 0 0 0 0
inst4|inst3|inst213 5 0 0 0 2 0 0 0 0 0 0 0 0
inst4|inst3|inst222|inst|lpm_add_sub_component|auto_generated 4 0 0 0 3 0 0 0 0 0 0 0 0
inst4|inst3|inst222|inst 4 0 0 0 3 0 0 0 0 0 0 0 0
inst4|inst3|inst222|inst15 4 0 0 0 3 0 0 0 0 0 0 0 0
inst4|inst3|inst222 5 0 0 0 3 0 0 0 0 0 0 0 0
inst4|inst3|inst234|inst2|lpm_add_sub_component|auto_generated 6 0 0 0 4 0 0 0 0 0 0 0 0
inst4|inst3|inst234|inst2 6 0 0 0 4 0 0 0 0 0 0 0 0
inst4|inst3|inst234|inst 5 0 0 0 4 0 0 0 0 0 0 0 0
inst4|inst3|inst234 7 0 0 0 4 0 0 0 0 0 0 0 0
inst4|inst3|inst202 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst200 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst206|inst 4 1 0 1 4 1 1 1 0 0 0 0 0
inst4|inst3|inst206|inst5 3 0 0 0 2 0 0 0 0 0 0 0 0
inst4|inst3|inst206 5 0 0 0 2 0 0 0 0 0 0 0 0
inst4|inst3|inst198 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst197 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst201|inst 4 1 0 1 4 1 1 1 0 0 0 0 0
inst4|inst3|inst201|inst5 3 0 0 0 2 0 0 0 0 0 0 0 0
inst4|inst3|inst201 5 0 0 0 2 0 0 0 0 0 0 0 0
inst4|inst3|inst210|inst|lpm_add_sub_component|auto_generated 4 0 0 0 3 0 0 0 0 0 0 0 0
inst4|inst3|inst210|inst 4 0 0 0 3 0 0 0 0 0 0 0 0
inst4|inst3|inst210|inst15 4 0 0 0 3 0 0 0 0 0 0 0 0
inst4|inst3|inst210 5 0 0 0 3 0 0 0 0 0 0 0 0
inst4|inst3|inst196 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst194 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst195|inst 4 1 0 1 4 1 1 1 0 0 0 0 0
inst4|inst3|inst195|inst5 3 0 0 0 2 0 0 0 0 0 0 0 0
inst4|inst3|inst195 5 0 0 0 2 0 0 0 0 0 0 0 0
inst4|inst3|inst193 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst192 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst190|inst 4 1 0 1 4 1 1 1 0 0 0 0 0
inst4|inst3|inst190|inst5 3 0 0 0 2 0 0 0 0 0 0 0 0
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inst4|inst3|inst20 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst31|inst 4 1 0 1 4 1 1 1 0 0 0 0 0
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inst4|inst3|inst19 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst18 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst26|inst 4 1 0 1 4 1 1 1 0 0 0 0 0
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inst4|inst3|inst26 5 0 0 0 2 0 0 0 0 0 0 0 0
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inst4|inst3|inst3 5 0 0 0 3 0 0 0 0 0 0 0 0
inst4|inst3|inst45|inst2|lpm_add_sub_component|auto_generated 6 0 0 0 4 0 0 0 0 0 0 0 0
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inst4|inst3|inst45|inst 5 0 0 0 4 0 0 0 0 0 0 0 0
inst4|inst3|inst45 7 0 0 0 4 0 0 0 0 0 0 0 0
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inst4|inst3|inst21|inst 4 1 0 1 4 1 1 1 0 0 0 0 0
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inst4|inst3|inst14 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst13 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst16|inst 4 1 0 1 4 1 1 1 0 0 0 0 0
inst4|inst3|inst16|inst5 3 0 0 0 2 0 0 0 0 0 0 0 0
inst4|inst3|inst16 5 0 0 0 2 0 0 0 0 0 0 0 0
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inst4|inst3|inst12 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst10 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst11|inst 4 1 0 1 4 1 1 1 0 0 0 0 0
inst4|inst3|inst11|inst5 3 0 0 0 2 0 0 0 0 0 0 0 0
inst4|inst3|inst11 5 0 0 0 2 0 0 0 0 0 0 0 0
inst4|inst3|inst9 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst8 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst6 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst5 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst3|inst7|inst 4 1 0 1 4 1 1 1 0 0 0 0 0
inst4|inst3|inst7|inst5 3 0 0 0 2 0 0 0 0 0 0 0 0
inst4|inst3|inst7 5 0 0 0 2 0 0 0 0 0 0 0 0
inst4|inst3|inst|inst|lpm_add_sub_component|auto_generated 4 0 0 0 3 0 0 0 0 0 0 0 0
inst4|inst3|inst|inst 4 0 0 0 3 0 0 0 0 0 0 0 0
inst4|inst3|inst|inst15 4 0 0 0 3 0 0 0 0 0 0 0 0
inst4|inst3|inst 5 0 0 0 3 0 0 0 0 0 0 0 0
inst4|inst3|inst2|inst2|lpm_add_sub_component|auto_generated 6 0 0 0 4 0 0 0 0 0 0 0 0
inst4|inst3|inst2|inst2 6 0 0 0 4 0 0 0 0 0 0 0 0
inst4|inst3|inst2|inst 5 0 0 0 4 0 0 0 0 0 0 0 0
inst4|inst3|inst2 7 0 0 0 4 0 0 0 0 0 0 0 0
inst4|inst3|inst46|inst3|lpm_add_sub_component|auto_generated 8 0 0 0 5 0 0 0 0 0 0 0 0
inst4|inst3|inst46|inst3 8 0 0 0 5 0 0 0 0 0 0 0 0
inst4|inst3|inst46|inst4 6 0 0 0 5 0 0 0 0 0 0 0 0
inst4|inst3|inst46 9 0 0 0 5 0 0 0 0 0 0 0 0
inst4|inst3|inst65|inst|lpm_add_sub_component|auto_generated 10 0 0 0 6 0 0 0 0 0 0 0 0
inst4|inst3|inst65|inst 10 0 0 0 6 0 0 0 0 0 0 0 0
inst4|inst3|inst65|inst2 7 0 0 0 6 0 0 0 0 0 0 0 0
inst4|inst3|inst65 11 0 0 0 6 0 0 0 0 0 0 0 0
inst4|inst3|inst254|inst3|lpm_add_sub_component|auto_generated 12 0 0 0 7 0 0 0 0 0 0 0 0
inst4|inst3|inst254|inst3 12 0 0 0 7 0 0 0 0 0 0 0 0
inst4|inst3|inst254|inst 8 0 0 0 7 0 0 0 0 0 0 0 0
inst4|inst3|inst254 13 0 0 0 7 0 0 0 0 0 0 0 0
inst4|inst3|inst256|inst2|lpm_add_sub_component|auto_generated 14 0 0 0 8 0 0 0 0 0 0 0 0
inst4|inst3|inst256|inst2 14 0 0 0 8 0 0 0 0 0 0 0 0
inst4|inst3|inst256|inst3 9 0 0 0 8 0 0 0 0 0 0 0 0
inst4|inst3|inst256 15 0 0 0 8 0 0 0 0 0 0 0 0
inst4|inst3 66 0 0 0 8 0 0 0 0 0 0 0 0
inst4|inst17|altaccumulate_component|accum_cell 11 0 0 0 16 0 0 0 0 0 0 0 0
inst4|inst17 11 0 0 0 16 0 0 0 0 0 0 0 0
inst4|inst7 0 0 0 0 16 0 0 0 0 0 0 0 0
inst4|inst29 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst28 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst33|lpm_counter_component|auto_generated 4 0 0 0 16 0 0 0 0 0 0 0 0
inst4|inst33 4 0 0 0 16 0 0 0 0 0 0 0 0
inst4|inst31|lpm_compare_component|auto_generated 33 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst31 33 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst 0 0 0 0 16 0 0 0 0 0 0 0 0
inst4|inst20 2 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst19|lpm_counter_component|auto_generated 4 0 0 0 16 0 0 0 0 0 0 0 0
inst4|inst19 4 0 0 0 16 0 0 0 0 0 0 0 0
inst4|inst23|lpm_compare_component|auto_generated 33 0 0 0 1 0 0 0 0 0 0 0 0
inst4|inst23 33 0 0 0 1 0 0 0 0 0 0 0 0
inst4 68 28 0 28 60 28 28 28 0 0 0 0 0
inst214|inst 2 0 0 0 1 0 0 0 0 0 0 0 0
inst214|inst2|lpm_compare_component|auto_generated 16 0 0 0 1 0 0 0 0 0 0 0 0
inst214|inst2 16 0 0 0 1 0 0 0 0 0 0 0 0
inst214|inst55|altlvds_rx_component|auto_generated|rx_outclock_buf 4 3 0 3 1 3 3 3 0 0 0 0 0
inst214|inst55|altlvds_rx_component|auto_generated 4 0 0 0 9 0 0 0 0 0 0 0 0
inst214|inst55 4 0 0 0 9 0 0 0 0 0 0 0 0
inst214 13 3 0 3 12 3 3 3 0 0 0 0 0
inst158|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst158|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst158|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst158|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst158|dcfifo_component|auto_generated|wrfull_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst158|dcfifo_component|auto_generated|wrfull_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst158|dcfifo_component|auto_generated|wrfull_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst158|dcfifo_component|auto_generated|wrfull_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst158|dcfifo_component|auto_generated|rdempty_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst158|dcfifo_component|auto_generated|rdempty_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst158|dcfifo_component|auto_generated|rdempty_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst158|dcfifo_component|auto_generated|rdempty_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst158|dcfifo_component|auto_generated|ws_dgrp|dffpipe9 6 0 0 0 5 0 0 0 0 0 0 0 0
inst158|dcfifo_component|auto_generated|ws_dgrp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst158|dcfifo_component|auto_generated|rs_dgwp|dffpipe6 6 0 0 0 5 0 0 0 0 0 0 0 0
inst158|dcfifo_component|auto_generated|rs_dgwp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst158|dcfifo_component|auto_generated|rdaclr 2 1 0 1 1 1 1 1 0 0 0 0 0
inst158|dcfifo_component|auto_generated|fifo_ram 21 0 0 0 8 0 0 0 0 0 0 0 0
inst158|dcfifo_component|auto_generated|wrptr_gp 2 0 0 0 5 0 0 0 0 0 0 0 0
inst158|dcfifo_component|auto_generated|wrptr_g1p 2 0 0 0 5 0 0 0 0 0 0 0 0
inst158|dcfifo_component|auto_generated|rdptr_g1p 3 0 0 0 5 0 0 0 0 0 0 0 0
inst158|dcfifo_component|auto_generated 12 0 0 0 8 0 0 0 0 0 0 0 0
inst158 12 2 0 2 8 2 2 2 0 0 0 0 0
inst181 9 0 0 0 8 0 0 0 0 0 0 0 0
inst213|inst 2 0 0 0 1 0 0 0 0 0 0 0 0
inst213|inst2|lpm_compare_component|auto_generated 16 0 0 0 1 0 0 0 0 0 0 0 0
inst213|inst2 16 0 0 0 1 0 0 0 0 0 0 0 0
inst213|inst55|altlvds_rx_component|auto_generated|rx_outclock_buf 4 3 0 3 1 3 3 3 0 0 0 0 0
inst213|inst55|altlvds_rx_component|auto_generated 4 0 0 0 9 0 0 0 0 0 0 0 0
inst213|inst55 4 0 0 0 9 0 0 0 0 0 0 0 0
inst213 13 3 0 3 12 3 3 3 0 0 0 0 0
inst182|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst182|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst182|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst182|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst182|dcfifo_component|auto_generated|wrfull_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst182|dcfifo_component|auto_generated|wrfull_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst182|dcfifo_component|auto_generated|wrfull_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst182|dcfifo_component|auto_generated|wrfull_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst182|dcfifo_component|auto_generated|rdempty_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst182|dcfifo_component|auto_generated|rdempty_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst182|dcfifo_component|auto_generated|rdempty_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst182|dcfifo_component|auto_generated|rdempty_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst182|dcfifo_component|auto_generated|ws_dgrp|dffpipe9 6 0 0 0 5 0 0 0 0 0 0 0 0
inst182|dcfifo_component|auto_generated|ws_dgrp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst182|dcfifo_component|auto_generated|rs_dgwp|dffpipe6 6 0 0 0 5 0 0 0 0 0 0 0 0
inst182|dcfifo_component|auto_generated|rs_dgwp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst182|dcfifo_component|auto_generated|rdaclr 2 1 0 1 1 1 1 1 0 0 0 0 0
inst182|dcfifo_component|auto_generated|fifo_ram 21 0 0 0 8 0 0 0 0 0 0 0 0
inst182|dcfifo_component|auto_generated|wrptr_gp 2 0 0 0 5 0 0 0 0 0 0 0 0
inst182|dcfifo_component|auto_generated|wrptr_g1p 2 0 0 0 5 0 0 0 0 0 0 0 0
inst182|dcfifo_component|auto_generated|rdptr_g1p 3 0 0 0 5 0 0 0 0 0 0 0 0
inst182|dcfifo_component|auto_generated 12 0 0 0 8 0 0 0 0 0 0 0 0
inst182 12 2 0 2 8 2 2 2 0 0 0 0 0
inst183 9 0 0 0 8 0 0 0 0 0 0 0 0
inst212|inst 2 0 0 0 1 0 0 0 0 0 0 0 0
inst212|inst2|lpm_compare_component|auto_generated 16 0 0 0 1 0 0 0 0 0 0 0 0
inst212|inst2 16 0 0 0 1 0 0 0 0 0 0 0 0
inst212|inst55|altlvds_rx_component|auto_generated|rx_outclock_buf 4 3 0 3 1 3 3 3 0 0 0 0 0
inst212|inst55|altlvds_rx_component|auto_generated 4 0 0 0 9 0 0 0 0 0 0 0 0
inst212|inst55 4 0 0 0 9 0 0 0 0 0 0 0 0
inst212 13 3 0 3 12 3 3 3 0 0 0 0 0
inst184|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst184|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst184|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst184|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst184|dcfifo_component|auto_generated|wrfull_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst184|dcfifo_component|auto_generated|wrfull_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst184|dcfifo_component|auto_generated|wrfull_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst184|dcfifo_component|auto_generated|wrfull_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst184|dcfifo_component|auto_generated|rdempty_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst184|dcfifo_component|auto_generated|rdempty_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst184|dcfifo_component|auto_generated|rdempty_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst184|dcfifo_component|auto_generated|rdempty_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst184|dcfifo_component|auto_generated|ws_dgrp|dffpipe9 6 0 0 0 5 0 0 0 0 0 0 0 0
inst184|dcfifo_component|auto_generated|ws_dgrp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst184|dcfifo_component|auto_generated|rs_dgwp|dffpipe6 6 0 0 0 5 0 0 0 0 0 0 0 0
inst184|dcfifo_component|auto_generated|rs_dgwp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst184|dcfifo_component|auto_generated|rdaclr 2 1 0 1 1 1 1 1 0 0 0 0 0
inst184|dcfifo_component|auto_generated|fifo_ram 21 0 0 0 8 0 0 0 0 0 0 0 0
inst184|dcfifo_component|auto_generated|wrptr_gp 2 0 0 0 5 0 0 0 0 0 0 0 0
inst184|dcfifo_component|auto_generated|wrptr_g1p 2 0 0 0 5 0 0 0 0 0 0 0 0
inst184|dcfifo_component|auto_generated|rdptr_g1p 3 0 0 0 5 0 0 0 0 0 0 0 0
inst184|dcfifo_component|auto_generated 12 0 0 0 8 0 0 0 0 0 0 0 0
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inst185 9 0 0 0 8 0 0 0 0 0 0 0 0
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inst211|inst2|lpm_compare_component|auto_generated 16 0 0 0 1 0 0 0 0 0 0 0 0
inst211|inst2 16 0 0 0 1 0 0 0 0 0 0 0 0
inst211|inst55|altlvds_rx_component|auto_generated|rx_outclock_buf 4 3 0 3 1 3 3 3 0 0 0 0 0
inst211|inst55|altlvds_rx_component|auto_generated 4 0 0 0 9 0 0 0 0 0 0 0 0
inst211|inst55 4 0 0 0 9 0 0 0 0 0 0 0 0
inst211 13 3 0 3 12 3 3 3 0 0 0 0 0
inst186|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst186|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst186|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst186|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst186|dcfifo_component|auto_generated|wrfull_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst186|dcfifo_component|auto_generated|wrfull_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst186|dcfifo_component|auto_generated|wrfull_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst186|dcfifo_component|auto_generated|wrfull_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst186|dcfifo_component|auto_generated|rdempty_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst186|dcfifo_component|auto_generated|rdempty_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst186|dcfifo_component|auto_generated|rdempty_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst186|dcfifo_component|auto_generated|rdempty_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst186|dcfifo_component|auto_generated|ws_dgrp|dffpipe9 6 0 0 0 5 0 0 0 0 0 0 0 0
inst186|dcfifo_component|auto_generated|ws_dgrp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst186|dcfifo_component|auto_generated|rs_dgwp|dffpipe6 6 0 0 0 5 0 0 0 0 0 0 0 0
inst186|dcfifo_component|auto_generated|rs_dgwp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst186|dcfifo_component|auto_generated|rdaclr 2 1 0 1 1 1 1 1 0 0 0 0 0
inst186|dcfifo_component|auto_generated|fifo_ram 21 0 0 0 8 0 0 0 0 0 0 0 0
inst186|dcfifo_component|auto_generated|wrptr_gp 2 0 0 0 5 0 0 0 0 0 0 0 0
inst186|dcfifo_component|auto_generated|wrptr_g1p 2 0 0 0 5 0 0 0 0 0 0 0 0
inst186|dcfifo_component|auto_generated|rdptr_g1p 3 0 0 0 5 0 0 0 0 0 0 0 0
inst186|dcfifo_component|auto_generated 12 0 0 0 8 0 0 0 0 0 0 0 0
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inst187 9 0 0 0 8 0 0 0 0 0 0 0 0
inst210|inst 2 0 0 0 1 0 0 0 0 0 0 0 0
inst210|inst2|lpm_compare_component|auto_generated 16 0 0 0 1 0 0 0 0 0 0 0 0
inst210|inst2 16 0 0 0 1 0 0 0 0 0 0 0 0
inst210|inst55|altlvds_rx_component|auto_generated|rx_outclock_buf 4 3 0 3 1 3 3 3 0 0 0 0 0
inst210|inst55|altlvds_rx_component|auto_generated 4 0 0 0 9 0 0 0 0 0 0 0 0
inst210|inst55 4 0 0 0 9 0 0 0 0 0 0 0 0
inst210 13 3 0 3 12 3 3 3 0 0 0 0 0
inst188|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst188|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst188|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst188|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst188|dcfifo_component|auto_generated|wrfull_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst188|dcfifo_component|auto_generated|wrfull_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst188|dcfifo_component|auto_generated|wrfull_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst188|dcfifo_component|auto_generated|wrfull_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst188|dcfifo_component|auto_generated|rdempty_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst188|dcfifo_component|auto_generated|rdempty_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst188|dcfifo_component|auto_generated|rdempty_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst188|dcfifo_component|auto_generated|rdempty_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst188|dcfifo_component|auto_generated|ws_dgrp|dffpipe9 6 0 0 0 5 0 0 0 0 0 0 0 0
inst188|dcfifo_component|auto_generated|ws_dgrp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst188|dcfifo_component|auto_generated|rs_dgwp|dffpipe6 6 0 0 0 5 0 0 0 0 0 0 0 0
inst188|dcfifo_component|auto_generated|rs_dgwp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst188|dcfifo_component|auto_generated|rdaclr 2 1 0 1 1 1 1 1 0 0 0 0 0
inst188|dcfifo_component|auto_generated|fifo_ram 21 0 0 0 8 0 0 0 0 0 0 0 0
inst188|dcfifo_component|auto_generated|wrptr_gp 2 0 0 0 5 0 0 0 0 0 0 0 0
inst188|dcfifo_component|auto_generated|wrptr_g1p 2 0 0 0 5 0 0 0 0 0 0 0 0
inst188|dcfifo_component|auto_generated|rdptr_g1p 3 0 0 0 5 0 0 0 0 0 0 0 0
inst188|dcfifo_component|auto_generated 12 0 0 0 8 0 0 0 0 0 0 0 0
inst188 12 2 0 2 8 2 2 2 0 0 0 0 0
inst189 9 0 0 0 8 0 0 0 0 0 0 0 0
inst94|inst 2 0 0 0 1 0 0 0 0 0 0 0 0
inst94|inst2|lpm_compare_component|auto_generated 16 0 0 0 1 0 0 0 0 0 0 0 0
inst94|inst2 16 0 0 0 1 0 0 0 0 0 0 0 0
inst94|inst55|altlvds_rx_component|auto_generated|rx_outclock_buf 4 3 0 3 1 3 3 3 0 0 0 0 0
inst94|inst55|altlvds_rx_component|auto_generated 4 0 0 0 9 0 0 0 0 0 0 0 0
inst94|inst55 4 0 0 0 9 0 0 0 0 0 0 0 0
inst94 13 3 0 3 12 3 3 3 0 0 0 0 0
inst190|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst190|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst190|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst190|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst190|dcfifo_component|auto_generated|wrfull_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst190|dcfifo_component|auto_generated|wrfull_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst190|dcfifo_component|auto_generated|wrfull_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst190|dcfifo_component|auto_generated|wrfull_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst190|dcfifo_component|auto_generated|rdempty_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst190|dcfifo_component|auto_generated|rdempty_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst190|dcfifo_component|auto_generated|rdempty_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst190|dcfifo_component|auto_generated|rdempty_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst190|dcfifo_component|auto_generated|ws_dgrp|dffpipe9 6 0 0 0 5 0 0 0 0 0 0 0 0
inst190|dcfifo_component|auto_generated|ws_dgrp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst190|dcfifo_component|auto_generated|rs_dgwp|dffpipe6 6 0 0 0 5 0 0 0 0 0 0 0 0
inst190|dcfifo_component|auto_generated|rs_dgwp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst190|dcfifo_component|auto_generated|rdaclr 2 1 0 1 1 1 1 1 0 0 0 0 0
inst190|dcfifo_component|auto_generated|fifo_ram 21 0 0 0 8 0 0 0 0 0 0 0 0
inst190|dcfifo_component|auto_generated|wrptr_gp 2 0 0 0 5 0 0 0 0 0 0 0 0
inst190|dcfifo_component|auto_generated|wrptr_g1p 2 0 0 0 5 0 0 0 0 0 0 0 0
inst190|dcfifo_component|auto_generated|rdptr_g1p 3 0 0 0 5 0 0 0 0 0 0 0 0
inst190|dcfifo_component|auto_generated 12 0 0 0 8 0 0 0 0 0 0 0 0
inst190 12 2 0 2 8 2 2 2 0 0 0 0 0
inst209 9 0 0 0 8 0 0 0 0 0 0 0 0
inst46|inst 2 0 0 0 1 0 0 0 0 0 0 0 0
inst46|inst2|lpm_compare_component|auto_generated 16 0 0 0 1 0 0 0 0 0 0 0 0
inst46|inst2 16 0 0 0 1 0 0 0 0 0 0 0 0
inst46|inst55|altlvds_rx_component|auto_generated|rx_outclock_buf 4 3 0 3 1 3 3 3 0 0 0 0 0
inst46|inst55|altlvds_rx_component|auto_generated 4 0 0 0 9 0 0 0 0 0 0 0 0
inst46|inst55 4 0 0 0 9 0 0 0 0 0 0 0 0
inst46 13 3 0 3 12 3 3 3 0 0 0 0 0
inst191|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst191|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst191|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst191|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst191|dcfifo_component|auto_generated|wrfull_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst191|dcfifo_component|auto_generated|wrfull_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst191|dcfifo_component|auto_generated|wrfull_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst191|dcfifo_component|auto_generated|wrfull_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst191|dcfifo_component|auto_generated|rdempty_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst191|dcfifo_component|auto_generated|rdempty_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst191|dcfifo_component|auto_generated|rdempty_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst191|dcfifo_component|auto_generated|rdempty_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst191|dcfifo_component|auto_generated|ws_dgrp|dffpipe9 6 0 0 0 5 0 0 0 0 0 0 0 0
inst191|dcfifo_component|auto_generated|ws_dgrp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst191|dcfifo_component|auto_generated|rs_dgwp|dffpipe6 6 0 0 0 5 0 0 0 0 0 0 0 0
inst191|dcfifo_component|auto_generated|rs_dgwp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst191|dcfifo_component|auto_generated|rdaclr 2 1 0 1 1 1 1 1 0 0 0 0 0
inst191|dcfifo_component|auto_generated|fifo_ram 21 0 0 0 8 0 0 0 0 0 0 0 0
inst191|dcfifo_component|auto_generated|wrptr_gp 2 0 0 0 5 0 0 0 0 0 0 0 0
inst191|dcfifo_component|auto_generated|wrptr_g1p 2 0 0 0 5 0 0 0 0 0 0 0 0
inst191|dcfifo_component|auto_generated|rdptr_g1p 3 0 0 0 5 0 0 0 0 0 0 0 0
inst191|dcfifo_component|auto_generated 12 0 0 0 8 0 0 0 0 0 0 0 0
inst191 12 2 0 2 8 2 2 2 0 0 0 0 0
inst192 9 0 0 0 8 0 0 0 0 0 0 0 0
inst53|inst 2 0 0 0 1 0 0 0 0 0 0 0 0
inst53|inst2|lpm_compare_component|auto_generated 16 0 0 0 1 0 0 0 0 0 0 0 0
inst53|inst2 16 0 0 0 1 0 0 0 0 0 0 0 0
inst53|inst55|altlvds_rx_component|auto_generated|rx_outclock_buf 4 3 0 3 1 3 3 3 0 0 0 0 0
inst53|inst55|altlvds_rx_component|auto_generated 4 0 0 0 9 0 0 0 0 0 0 0 0
inst53|inst55 4 0 0 0 9 0 0 0 0 0 0 0 0
inst53 13 3 0 3 12 3 3 3 0 0 0 0 0
inst207|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst207|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst207|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst207|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst207|dcfifo_component|auto_generated|wrfull_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst207|dcfifo_component|auto_generated|wrfull_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst207|dcfifo_component|auto_generated|wrfull_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst207|dcfifo_component|auto_generated|wrfull_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst207|dcfifo_component|auto_generated|rdempty_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst207|dcfifo_component|auto_generated|rdempty_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst207|dcfifo_component|auto_generated|rdempty_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst207|dcfifo_component|auto_generated|rdempty_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst207|dcfifo_component|auto_generated|ws_dgrp|dffpipe9 6 0 0 0 5 0 0 0 0 0 0 0 0
inst207|dcfifo_component|auto_generated|ws_dgrp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst207|dcfifo_component|auto_generated|rs_dgwp|dffpipe6 6 0 0 0 5 0 0 0 0 0 0 0 0
inst207|dcfifo_component|auto_generated|rs_dgwp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst207|dcfifo_component|auto_generated|rdaclr 2 1 0 1 1 1 1 1 0 0 0 0 0
inst207|dcfifo_component|auto_generated|fifo_ram 21 0 0 0 8 0 0 0 0 0 0 0 0
inst207|dcfifo_component|auto_generated|wrptr_gp 2 0 0 0 5 0 0 0 0 0 0 0 0
inst207|dcfifo_component|auto_generated|wrptr_g1p 2 0 0 0 5 0 0 0 0 0 0 0 0
inst207|dcfifo_component|auto_generated|rdptr_g1p 3 0 0 0 5 0 0 0 0 0 0 0 0
inst207|dcfifo_component|auto_generated 12 0 0 0 8 0 0 0 0 0 0 0 0
inst207 12 2 0 2 8 2 2 2 0 0 0 0 0
inst208 9 0 0 0 8 0 0 0 0 0 0 0 0
inst101|inst 2 0 0 0 1 0 0 0 0 0 0 0 0
inst101|inst2|lpm_compare_component|auto_generated 16 0 0 0 1 0 0 0 0 0 0 0 0
inst101|inst2 16 0 0 0 1 0 0 0 0 0 0 0 0
inst101|inst55|altlvds_rx_component|auto_generated|rx_outclock_buf 4 3 0 3 1 3 3 3 0 0 0 0 0
inst101|inst55|altlvds_rx_component|auto_generated 4 0 0 0 9 0 0 0 0 0 0 0 0
inst101|inst55 4 0 0 0 9 0 0 0 0 0 0 0 0
inst101 13 3 0 3 12 3 3 3 0 0 0 0 0
inst102|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst102|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst102|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst102|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst102|dcfifo_component|auto_generated|wrfull_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst102|dcfifo_component|auto_generated|wrfull_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst102|dcfifo_component|auto_generated|wrfull_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst102|dcfifo_component|auto_generated|wrfull_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst102|dcfifo_component|auto_generated|rdempty_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst102|dcfifo_component|auto_generated|rdempty_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst102|dcfifo_component|auto_generated|rdempty_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst102|dcfifo_component|auto_generated|rdempty_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst102|dcfifo_component|auto_generated|ws_dgrp|dffpipe9 6 0 0 0 5 0 0 0 0 0 0 0 0
inst102|dcfifo_component|auto_generated|ws_dgrp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst102|dcfifo_component|auto_generated|rs_dgwp|dffpipe6 6 0 0 0 5 0 0 0 0 0 0 0 0
inst102|dcfifo_component|auto_generated|rs_dgwp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst102|dcfifo_component|auto_generated|rdaclr 2 1 0 1 1 1 1 1 0 0 0 0 0
inst102|dcfifo_component|auto_generated|fifo_ram 21 0 0 0 8 0 0 0 0 0 0 0 0
inst102|dcfifo_component|auto_generated|wrptr_gp 2 0 0 0 5 0 0 0 0 0 0 0 0
inst102|dcfifo_component|auto_generated|wrptr_g1p 2 0 0 0 5 0 0 0 0 0 0 0 0
inst102|dcfifo_component|auto_generated|rdptr_g1p 3 0 0 0 5 0 0 0 0 0 0 0 0
inst102|dcfifo_component|auto_generated 12 0 0 0 8 0 0 0 0 0 0 0 0
inst102 12 2 0 2 8 2 2 2 0 0 0 0 0
inst138 9 0 0 0 8 0 0 0 0 0 0 0 0
inst76|inst 2 0 0 0 1 0 0 0 0 0 0 0 0
inst76|inst2|lpm_compare_component|auto_generated 16 0 0 0 1 0 0 0 0 0 0 0 0
inst76|inst2 16 0 0 0 1 0 0 0 0 0 0 0 0
inst76|inst55|altlvds_rx_component|auto_generated|rx_outclock_buf 4 3 0 3 1 3 3 3 0 0 0 0 0
inst76|inst55|altlvds_rx_component|auto_generated 4 0 0 0 9 0 0 0 0 0 0 0 0
inst76|inst55 4 0 0 0 9 0 0 0 0 0 0 0 0
inst76 13 3 0 3 12 3 3 3 0 0 0 0 0
inst109|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst109|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst109|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst109|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst109|dcfifo_component|auto_generated|wrfull_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst109|dcfifo_component|auto_generated|wrfull_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst109|dcfifo_component|auto_generated|wrfull_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst109|dcfifo_component|auto_generated|wrfull_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst109|dcfifo_component|auto_generated|rdempty_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst109|dcfifo_component|auto_generated|rdempty_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst109|dcfifo_component|auto_generated|rdempty_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst109|dcfifo_component|auto_generated|rdempty_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst109|dcfifo_component|auto_generated|ws_dgrp|dffpipe9 6 0 0 0 5 0 0 0 0 0 0 0 0
inst109|dcfifo_component|auto_generated|ws_dgrp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst109|dcfifo_component|auto_generated|rs_dgwp|dffpipe6 6 0 0 0 5 0 0 0 0 0 0 0 0
inst109|dcfifo_component|auto_generated|rs_dgwp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst109|dcfifo_component|auto_generated|rdaclr 2 1 0 1 1 1 1 1 0 0 0 0 0
inst109|dcfifo_component|auto_generated|fifo_ram 21 0 0 0 8 0 0 0 0 0 0 0 0
inst109|dcfifo_component|auto_generated|wrptr_gp 2 0 0 0 5 0 0 0 0 0 0 0 0
inst109|dcfifo_component|auto_generated|wrptr_g1p 2 0 0 0 5 0 0 0 0 0 0 0 0
inst109|dcfifo_component|auto_generated|rdptr_g1p 3 0 0 0 5 0 0 0 0 0 0 0 0
inst109|dcfifo_component|auto_generated 12 0 0 0 8 0 0 0 0 0 0 0 0
inst109 12 2 0 2 8 2 2 2 0 0 0 0 0
inst141 9 0 0 0 8 0 0 0 0 0 0 0 0
inst52|inst 2 0 0 0 1 0 0 0 0 0 0 0 0
inst52|inst2|lpm_compare_component|auto_generated 16 0 0 0 1 0 0 0 0 0 0 0 0
inst52|inst2 16 0 0 0 1 0 0 0 0 0 0 0 0
inst52|inst55|altlvds_rx_component|auto_generated|rx_outclock_buf 4 3 0 3 1 3 3 3 0 0 0 0 0
inst52|inst55|altlvds_rx_component|auto_generated 4 0 0 0 9 0 0 0 0 0 0 0 0
inst52|inst55 4 0 0 0 9 0 0 0 0 0 0 0 0
inst52 13 3 0 3 12 3 3 3 0 0 0 0 0
inst161|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst161|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst161|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst161|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst161|dcfifo_component|auto_generated|wrfull_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst161|dcfifo_component|auto_generated|wrfull_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst161|dcfifo_component|auto_generated|wrfull_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst161|dcfifo_component|auto_generated|wrfull_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst161|dcfifo_component|auto_generated|rdempty_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst161|dcfifo_component|auto_generated|rdempty_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst161|dcfifo_component|auto_generated|rdempty_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst161|dcfifo_component|auto_generated|rdempty_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst161|dcfifo_component|auto_generated|ws_dgrp|dffpipe9 6 0 0 0 5 0 0 0 0 0 0 0 0
inst161|dcfifo_component|auto_generated|ws_dgrp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst161|dcfifo_component|auto_generated|rs_dgwp|dffpipe6 6 0 0 0 5 0 0 0 0 0 0 0 0
inst161|dcfifo_component|auto_generated|rs_dgwp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst161|dcfifo_component|auto_generated|rdaclr 2 1 0 1 1 1 1 1 0 0 0 0 0
inst161|dcfifo_component|auto_generated|fifo_ram 21 0 0 0 8 0 0 0 0 0 0 0 0
inst161|dcfifo_component|auto_generated|wrptr_gp 2 0 0 0 5 0 0 0 0 0 0 0 0
inst161|dcfifo_component|auto_generated|wrptr_g1p 2 0 0 0 5 0 0 0 0 0 0 0 0
inst161|dcfifo_component|auto_generated|rdptr_g1p 3 0 0 0 5 0 0 0 0 0 0 0 0
inst161|dcfifo_component|auto_generated 12 0 0 0 8 0 0 0 0 0 0 0 0
inst161 12 2 0 2 8 2 2 2 0 0 0 0 0
inst162 9 0 0 0 8 0 0 0 0 0 0 0 0
inst72|inst 2 0 0 0 1 0 0 0 0 0 0 0 0
inst72|inst2|lpm_compare_component|auto_generated 16 0 0 0 1 0 0 0 0 0 0 0 0
inst72|inst2 16 0 0 0 1 0 0 0 0 0 0 0 0
inst72|inst55|altlvds_rx_component|auto_generated|rx_outclock_buf 4 3 0 3 1 3 3 3 0 0 0 0 0
inst72|inst55|altlvds_rx_component|auto_generated 4 0 0 0 9 0 0 0 0 0 0 0 0
inst72|inst55 4 0 0 0 9 0 0 0 0 0 0 0 0
inst72 13 3 0 3 12 3 3 3 0 0 0 0 0
inst110|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst110|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst110|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst110|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst110|dcfifo_component|auto_generated|wrfull_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst110|dcfifo_component|auto_generated|wrfull_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst110|dcfifo_component|auto_generated|wrfull_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst110|dcfifo_component|auto_generated|wrfull_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst110|dcfifo_component|auto_generated|rdempty_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst110|dcfifo_component|auto_generated|rdempty_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst110|dcfifo_component|auto_generated|rdempty_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst110|dcfifo_component|auto_generated|rdempty_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst110|dcfifo_component|auto_generated|ws_dgrp|dffpipe9 6 0 0 0 5 0 0 0 0 0 0 0 0
inst110|dcfifo_component|auto_generated|ws_dgrp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst110|dcfifo_component|auto_generated|rs_dgwp|dffpipe6 6 0 0 0 5 0 0 0 0 0 0 0 0
inst110|dcfifo_component|auto_generated|rs_dgwp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst110|dcfifo_component|auto_generated|rdaclr 2 1 0 1 1 1 1 1 0 0 0 0 0
inst110|dcfifo_component|auto_generated|fifo_ram 21 0 0 0 8 0 0 0 0 0 0 0 0
inst110|dcfifo_component|auto_generated|wrptr_gp 2 0 0 0 5 0 0 0 0 0 0 0 0
inst110|dcfifo_component|auto_generated|wrptr_g1p 2 0 0 0 5 0 0 0 0 0 0 0 0
inst110|dcfifo_component|auto_generated|rdptr_g1p 3 0 0 0 5 0 0 0 0 0 0 0 0
inst110|dcfifo_component|auto_generated 12 0 0 0 8 0 0 0 0 0 0 0 0
inst110 12 2 0 2 8 2 2 2 0 0 0 0 0
inst147 9 0 0 0 8 0 0 0 0 0 0 0 0
inst69|inst 2 0 0 0 1 0 0 0 0 0 0 0 0
inst69|inst2|lpm_compare_component|auto_generated 16 0 0 0 1 0 0 0 0 0 0 0 0
inst69|inst2 16 0 0 0 1 0 0 0 0 0 0 0 0
inst69|inst55|altlvds_rx_component|auto_generated|rx_outclock_buf 4 3 0 3 1 3 3 3 0 0 0 0 0
inst69|inst55|altlvds_rx_component|auto_generated 4 0 0 0 9 0 0 0 0 0 0 0 0
inst69|inst55 4 0 0 0 9 0 0 0 0 0 0 0 0
inst69 13 3 0 3 12 3 3 3 0 0 0 0 0
inst111|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst111|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst111|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst111|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst111|dcfifo_component|auto_generated|wrfull_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst111|dcfifo_component|auto_generated|wrfull_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst111|dcfifo_component|auto_generated|wrfull_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst111|dcfifo_component|auto_generated|wrfull_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst111|dcfifo_component|auto_generated|rdempty_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst111|dcfifo_component|auto_generated|rdempty_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst111|dcfifo_component|auto_generated|rdempty_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst111|dcfifo_component|auto_generated|rdempty_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst111|dcfifo_component|auto_generated|ws_dgrp|dffpipe9 6 0 0 0 5 0 0 0 0 0 0 0 0
inst111|dcfifo_component|auto_generated|ws_dgrp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst111|dcfifo_component|auto_generated|rs_dgwp|dffpipe6 6 0 0 0 5 0 0 0 0 0 0 0 0
inst111|dcfifo_component|auto_generated|rs_dgwp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst111|dcfifo_component|auto_generated|rdaclr 2 1 0 1 1 1 1 1 0 0 0 0 0
inst111|dcfifo_component|auto_generated|fifo_ram 21 0 0 0 8 0 0 0 0 0 0 0 0
inst111|dcfifo_component|auto_generated|wrptr_gp 2 0 0 0 5 0 0 0 0 0 0 0 0
inst111|dcfifo_component|auto_generated|wrptr_g1p 2 0 0 0 5 0 0 0 0 0 0 0 0
inst111|dcfifo_component|auto_generated|rdptr_g1p 3 0 0 0 5 0 0 0 0 0 0 0 0
inst111|dcfifo_component|auto_generated 12 0 0 0 8 0 0 0 0 0 0 0 0
inst111 12 2 0 2 8 2 2 2 0 0 0 0 0
inst155 9 0 0 0 8 0 0 0 0 0 0 0 0
inst66|inst 2 0 0 0 1 0 0 0 0 0 0 0 0
inst66|inst2|lpm_compare_component|auto_generated 16 0 0 0 1 0 0 0 0 0 0 0 0
inst66|inst2 16 0 0 0 1 0 0 0 0 0 0 0 0
inst66|inst55|altlvds_rx_component|auto_generated|rx_outclock_buf 4 3 0 3 1 3 3 3 0 0 0 0 0
inst66|inst55|altlvds_rx_component|auto_generated 4 0 0 0 9 0 0 0 0 0 0 0 0
inst66|inst55 4 0 0 0 9 0 0 0 0 0 0 0 0
inst66 13 3 0 3 12 3 3 3 0 0 0 0 0
inst112|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst112|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst112|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst112|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst112|dcfifo_component|auto_generated|wrfull_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst112|dcfifo_component|auto_generated|wrfull_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst112|dcfifo_component|auto_generated|wrfull_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst112|dcfifo_component|auto_generated|wrfull_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst112|dcfifo_component|auto_generated|rdempty_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst112|dcfifo_component|auto_generated|rdempty_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst112|dcfifo_component|auto_generated|rdempty_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst112|dcfifo_component|auto_generated|rdempty_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst112|dcfifo_component|auto_generated|ws_dgrp|dffpipe9 6 0 0 0 5 0 0 0 0 0 0 0 0
inst112|dcfifo_component|auto_generated|ws_dgrp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst112|dcfifo_component|auto_generated|rs_dgwp|dffpipe6 6 0 0 0 5 0 0 0 0 0 0 0 0
inst112|dcfifo_component|auto_generated|rs_dgwp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst112|dcfifo_component|auto_generated|rdaclr 2 1 0 1 1 1 1 1 0 0 0 0 0
inst112|dcfifo_component|auto_generated|fifo_ram 21 0 0 0 8 0 0 0 0 0 0 0 0
inst112|dcfifo_component|auto_generated|wrptr_gp 2 0 0 0 5 0 0 0 0 0 0 0 0
inst112|dcfifo_component|auto_generated|wrptr_g1p 2 0 0 0 5 0 0 0 0 0 0 0 0
inst112|dcfifo_component|auto_generated|rdptr_g1p 3 0 0 0 5 0 0 0 0 0 0 0 0
inst112|dcfifo_component|auto_generated 12 0 0 0 8 0 0 0 0 0 0 0 0
inst112 12 2 0 2 8 2 2 2 0 0 0 0 0
inst156 9 0 0 0 8 0 0 0 0 0 0 0 0
inst63|inst 2 0 0 0 1 0 0 0 0 0 0 0 0
inst63|inst2|lpm_compare_component|auto_generated 16 0 0 0 1 0 0 0 0 0 0 0 0
inst63|inst2 16 0 0 0 1 0 0 0 0 0 0 0 0
inst63|inst55|altlvds_rx_component|auto_generated|rx_outclock_buf 4 3 0 3 1 3 3 3 0 0 0 0 0
inst63|inst55|altlvds_rx_component|auto_generated 4 0 0 0 9 0 0 0 0 0 0 0 0
inst63|inst55 4 0 0 0 9 0 0 0 0 0 0 0 0
inst63 13 3 0 3 12 3 3 3 0 0 0 0 0
inst113|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst113|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst113|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst113|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst113|dcfifo_component|auto_generated|wrfull_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst113|dcfifo_component|auto_generated|wrfull_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst113|dcfifo_component|auto_generated|wrfull_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst113|dcfifo_component|auto_generated|wrfull_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst113|dcfifo_component|auto_generated|rdempty_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst113|dcfifo_component|auto_generated|rdempty_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst113|dcfifo_component|auto_generated|rdempty_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst113|dcfifo_component|auto_generated|rdempty_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst113|dcfifo_component|auto_generated|ws_dgrp|dffpipe9 6 0 0 0 5 0 0 0 0 0 0 0 0
inst113|dcfifo_component|auto_generated|ws_dgrp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst113|dcfifo_component|auto_generated|rs_dgwp|dffpipe6 6 0 0 0 5 0 0 0 0 0 0 0 0
inst113|dcfifo_component|auto_generated|rs_dgwp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst113|dcfifo_component|auto_generated|rdaclr 2 1 0 1 1 1 1 1 0 0 0 0 0
inst113|dcfifo_component|auto_generated|fifo_ram 21 0 0 0 8 0 0 0 0 0 0 0 0
inst113|dcfifo_component|auto_generated|wrptr_gp 2 0 0 0 5 0 0 0 0 0 0 0 0
inst113|dcfifo_component|auto_generated|wrptr_g1p 2 0 0 0 5 0 0 0 0 0 0 0 0
inst113|dcfifo_component|auto_generated|rdptr_g1p 3 0 0 0 5 0 0 0 0 0 0 0 0
inst113|dcfifo_component|auto_generated 12 0 0 0 8 0 0 0 0 0 0 0 0
inst113 12 2 0 2 8 2 2 2 0 0 0 0 0
inst179 9 0 0 0 8 0 0 0 0 0 0 0 0
inst44|inst 2 0 0 0 1 0 0 0 0 0 0 0 0
inst44|inst2|lpm_compare_component|auto_generated 16 0 0 0 1 0 0 0 0 0 0 0 0
inst44|inst2 16 0 0 0 1 0 0 0 0 0 0 0 0
inst44|inst55|altlvds_rx_component|auto_generated|rx_outclock_buf 4 3 0 3 1 3 3 3 0 0 0 0 0
inst44|inst55|altlvds_rx_component|auto_generated 4 0 0 0 9 0 0 0 0 0 0 0 0
inst44|inst55 4 0 0 0 9 0 0 0 0 0 0 0 0
inst44 13 3 0 3 12 3 3 3 0 0 0 0 0
inst159|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst159|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst159|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst159|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst159|dcfifo_component|auto_generated|wrfull_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst159|dcfifo_component|auto_generated|wrfull_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst159|dcfifo_component|auto_generated|wrfull_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst159|dcfifo_component|auto_generated|wrfull_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst159|dcfifo_component|auto_generated|rdempty_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst159|dcfifo_component|auto_generated|rdempty_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst159|dcfifo_component|auto_generated|rdempty_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst159|dcfifo_component|auto_generated|rdempty_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst159|dcfifo_component|auto_generated|ws_dgrp|dffpipe9 6 0 0 0 5 0 0 0 0 0 0 0 0
inst159|dcfifo_component|auto_generated|ws_dgrp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst159|dcfifo_component|auto_generated|rs_dgwp|dffpipe6 6 0 0 0 5 0 0 0 0 0 0 0 0
inst159|dcfifo_component|auto_generated|rs_dgwp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst159|dcfifo_component|auto_generated|rdaclr 2 1 0 1 1 1 1 1 0 0 0 0 0
inst159|dcfifo_component|auto_generated|fifo_ram 21 0 0 0 8 0 0 0 0 0 0 0 0
inst159|dcfifo_component|auto_generated|wrptr_gp 2 0 0 0 5 0 0 0 0 0 0 0 0
inst159|dcfifo_component|auto_generated|wrptr_g1p 2 0 0 0 5 0 0 0 0 0 0 0 0
inst159|dcfifo_component|auto_generated|rdptr_g1p 3 0 0 0 5 0 0 0 0 0 0 0 0
inst159|dcfifo_component|auto_generated 12 0 0 0 8 0 0 0 0 0 0 0 0
inst159 12 2 0 2 8 2 2 2 0 0 0 0 0
inst160 9 0 0 0 8 0 0 0 0 0 0 0 0
inst82 3 0 0 0 6 0 0 0 0 0 0 0 0
inst36|inst31 14 0 0 0 13 0 0 0 0 0 0 0 0
inst36|inst3|lpm_counter_component|auto_generated 3 0 0 0 13 0 0 0 0 0 0 0 0
inst36|inst3 3 1 0 1 13 1 1 1 0 0 0 0 0
inst36|inst33|lpm_mux_component|auto_generated 28 0 0 0 13 0 0 0 0 0 0 0 0
inst36|inst33 28 0 0 0 13 0 0 0 0 0 0 0 0
inst36|inst32 14 0 0 0 13 0 0 0 0 0 0 0 0
inst36|inst86|altsyncram_component|auto_generated 287 0 0 0 256 0 0 0 0 0 0 0 0
inst36|inst86 287 0 0 0 256 0 0 0 0 0 0 0 0
inst36|inst19|lpm_counter_component|auto_generated 3 0 0 0 24 0 0 0 0 0 0 0 0
inst36|inst19 3 0 0 0 24 0 0 0 0 0 0 0 0
inst36|inst17 2 0 0 0 1 0 0 0 0 0 0 0 0
inst36|inst29 33 0 0 0 32 0 0 0 0 0 0 0 0
inst36|inst30 33 0 0 0 32 0 0 0 0 0 0 0 0
inst36|inst21|lpm_compare_component|auto_generated 34 0 0 0 1 0 0 0 0 0 0 0 0
inst36|inst21 34 0 0 0 1 0 0 0 0 0 0 0 0
inst36|inst27 33 0 0 0 32 0 0 0 0 0 0 0 0
inst36|inst|lpm_counter_component|auto_generated 3 0 0 0 8 0 0 0 0 0 0 0 0
inst36|inst 3 0 0 0 8 0 0 0 0 0 0 0 0
inst36|inst1|lpm_compare_component|auto_generated 17 0 0 0 1 0 0 0 0 0 0 0 0
inst36|inst1 17 0 0 0 1 0 0 0 0 0 0 0 0
inst36|inst2|lpm_counter_component|auto_generated 3 0 0 0 13 0 0 0 0 0 0 0 0
inst36|inst2 3 0 0 0 13 0 0 0 0 0 0 0 0
inst36|inst10|lpm_compare_component|auto_generated 27 0 0 0 1 0 0 0 0 0 0 0 0
inst36|inst10 27 0 0 0 1 0 0 0 0 0 0 0 0
inst36|inst4 2 0 0 0 1 0 0 0 0 0 0 0 0
inst36 371 18 0 18 273 18 18 18 0 0 0 0 0
inst57 392 131 10 131 269 131 131 131 32 0 0 0 0
inst81|inst7 33 0 0 0 32 0 0 0 0 0 0 0 0
inst81|inst8 33 0 0 0 32 0 0 0 0 0 0 0 0
inst81|inst3 33 0 0 0 32 0 0 0 0 0 0 0 0
inst81|inst5 33 0 0 0 32 0 0 0 0 0 0 0 0
inst81|inst1 33 0 0 0 32 0 0 0 0 0 0 0 0
inst81|inst2 33 0 0 0 32 0 0 0 0 0 0 0 0
inst81|inst22 33 0 0 0 32 0 0 0 0 0 0 0 0
inst81|inst23 33 0 0 0 32 0 0 0 0 0 0 0 0
inst81|inst19 33 0 0 0 32 0 0 0 0 0 0 0 0
inst81|inst20 33 0 0 0 32 0 0 0 0 0 0 0 0
inst81|inst16 33 0 0 0 32 0 0 0 0 0 0 0 0
inst81|inst17 33 0 0 0 32 0 0 0 0 0 0 0 0
inst81|inst13 33 0 0 0 32 0 0 0 0 0 0 0 0
inst81|inst14 33 0 0 0 32 0 0 0 0 0 0 0 0
inst81|inst10 33 0 0 0 32 0 0 0 0 0 0 0 0
inst81|inst11 33 0 0 0 32 0 0 0 0 0 0 0 0
inst81|inst61 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst62 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst58 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst59 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst55 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst56 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst52 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst53 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst49 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst50 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst46 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst47 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst43 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst44 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst40 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst41 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst37 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst38 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst34 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst35 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst31 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst32 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst28 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst29 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst25 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst26 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81 271 41 1 41 269 41 41 41 0 0 0 0 0
inst13 2 0 0 0 10 0 0 0 0 0 0 0 0
inst14 2 0 0 0 1 0 0 0 0 0 0 0 0
inst15 2 0 0 0 1 0 0 0 0 0 0 0 0
inst22 3 2 0 2 3 2 2 2 0 0 0 0 0
inst16 2 0 0 0 1 0 0 0 0 0 0 0 0
inst17 2 0 0 0 1 0 0 0 0 0 0 0 0
inst2|address_cnt|auto_generated 9 0 0 0 6 0 0 0 0 0 0 0 0
inst2|comp|auto_generated 20 0 0 0 1 0 0 0 0 0 0 0 0
inst2 54 1 1 1 33 1 1 1 2 0 0 0 2