Hierarchy Input Constant Input Unused Input Floating Input Output Constant Output Unused Output Floating Output Bidir Constant Bidir Unused Bidir Input only Bidir Output only Bidir
inst7|lpm_counter_component|auto_generated 1 0 0 0 25 0 0 0 0 0 0 0 0
inst7 1 25 0 25 25 25 25 25 0 0 0 0 0
inst74|lpm_counter_component|auto_generated 1 0 0 0 16 0 0 0 0 0 0 0 0
inst74 1 0 0 0 16 0 0 0 0 0 0 0 0
inst42 17 0 0 0 16 0 0 0 0 0 0 0 0
inst100|lpm_counter_component|auto_generated 1 0 0 0 16 0 0 0 0 0 0 0 0
inst100 1 0 0 0 16 0 0 0 0 0 0 0 0
inst97 17 0 0 0 16 0 0 0 0 0 0 0 0
inst62 2 0 0 0 1 0 0 0 0 0 0 0 0
inst52 2 0 0 0 1 0 0 0 0 0 0 0 0
inst18|lpm_counter_component|auto_generated 1 0 0 0 25 0 0 0 0 0 0 0 0
inst18 1 0 0 0 25 0 0 0 0 0 0 0 0
inst|lpm_counter_component|auto_generated 1 0 0 0 24 0 0 0 0 0 0 0 0
inst 1 0 0 0 24 0 0 0 0 0 0 0 0
inst19|lpm_counter_component|auto_generated 3 0 0 0 24 0 0 0 0 0 0 0 0
inst19 3 0 0 0 24 0 0 0 0 0 0 0 0
inst44 2 1 0 1 1 1 1 1 0 0 0 0 0
inst35|status_constant_lpm_constant_sb9_component 0 32 0 32 32 32 32 32 0 0 0 0 0
inst35 0 0 0 0 32 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated|wrfull_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated|wrfull_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated|wrfull_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated|wrfull_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated|rdempty_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated|rdempty_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated|rdempty_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated|rdempty_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated|ws_dgrp|dffpipe9 6 0 0 0 5 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated|ws_dgrp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated|rs_dgwp|dffpipe9 6 0 0 0 5 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated|rs_dgwp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated|rdaclr 2 1 0 1 1 1 1 1 0 0 0 0 0
inst98|dcfifo_component|auto_generated|fifo_ram 29 0 0 0 16 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated|wrptr_gp 2 0 0 0 5 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated|wrptr_g1p 2 0 0 0 5 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated|rdptr_g1p 3 0 0 0 5 0 0 0 0 0 0 0 0
inst98|dcfifo_component|auto_generated 20 0 0 0 16 0 0 0 0 0 0 0 0
inst98 20 2 0 2 16 2 2 2 0 0 0 0 0
inst10|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst10|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst10|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst10|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
inst10|dcfifo_component|auto_generated|wrfull_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst10|dcfifo_component|auto_generated|wrfull_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst10|dcfifo_component|auto_generated|wrfull_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst10|dcfifo_component|auto_generated|wrfull_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst10|dcfifo_component|auto_generated|rdempty_eq_comp_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst10|dcfifo_component|auto_generated|rdempty_eq_comp_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst10|dcfifo_component|auto_generated|rdempty_eq_comp1_msb 4 0 0 0 1 0 0 0 0 0 0 0 0
inst10|dcfifo_component|auto_generated|rdempty_eq_comp1_lsb 6 0 0 0 1 0 0 0 0 0 0 0 0
inst10|dcfifo_component|auto_generated|ws_dgrp|dffpipe9 6 0 0 0 5 0 0 0 0 0 0 0 0
inst10|dcfifo_component|auto_generated|ws_dgrp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst10|dcfifo_component|auto_generated|rs_dgwp|dffpipe9 6 0 0 0 5 0 0 0 0 0 0 0 0
inst10|dcfifo_component|auto_generated|rs_dgwp 6 0 0 0 5 0 0 0 0 0 0 0 0
inst10|dcfifo_component|auto_generated|rdaclr 2 1 0 1 1 1 1 1 0 0 0 0 0
inst10|dcfifo_component|auto_generated|fifo_ram 29 0 0 0 16 0 0 0 0 0 0 0 0
inst10|dcfifo_component|auto_generated|wrptr_gp 2 0 0 0 5 0 0 0 0 0 0 0 0
inst10|dcfifo_component|auto_generated|wrptr_g1p 2 0 0 0 5 0 0 0 0 0 0 0 0
inst10|dcfifo_component|auto_generated|rdptr_g1p 3 0 0 0 5 0 0 0 0 0 0 0 0
inst10|dcfifo_component|auto_generated 20 0 0 0 16 0 0 0 0 0 0 0 0
inst10 20 2 0 2 16 2 2 2 0 0 0 0 0
inst36|inst31 14 0 0 0 13 0 0 0 0 0 0 0 0
inst36|inst3|lpm_counter_component|auto_generated 3 0 0 0 13 0 0 0 0 0 0 0 0
inst36|inst3 3 1 0 1 13 1 1 1 0 0 0 0 0
inst36|inst33|lpm_mux_component|auto_generated 28 0 0 0 13 0 0 0 0 0 0 0 0
inst36|inst33 28 0 0 0 13 0 0 0 0 0 0 0 0
inst36|inst32 14 0 0 0 13 0 0 0 0 0 0 0 0
inst36|inst86|altsyncram_component|auto_generated 287 0 0 0 256 0 0 0 0 0 0 0 0
inst36|inst86 287 0 0 0 256 0 0 0 0 0 0 0 0
inst36|inst19|lpm_counter_component|auto_generated 3 0 0 0 24 0 0 0 0 0 0 0 0
inst36|inst19 3 0 0 0 24 0 0 0 0 0 0 0 0
inst36|inst17 2 0 0 0 1 0 0 0 0 0 0 0 0
inst36|inst29 33 0 0 0 32 0 0 0 0 0 0 0 0
inst36|inst30 33 0 0 0 32 0 0 0 0 0 0 0 0
inst36|inst21|lpm_compare_component|auto_generated 34 0 0 0 1 0 0 0 0 0 0 0 0
inst36|inst21 34 0 0 0 1 0 0 0 0 0 0 0 0
inst36|inst27 33 0 0 0 32 0 0 0 0 0 0 0 0
inst36|inst|lpm_counter_component|auto_generated 3 0 0 0 8 0 0 0 0 0 0 0 0
inst36|inst 3 0 0 0 8 0 0 0 0 0 0 0 0
inst36|inst1|lpm_compare_component|auto_generated 17 0 0 0 1 0 0 0 0 0 0 0 0
inst36|inst1 17 0 0 0 1 0 0 0 0 0 0 0 0
inst36|inst2|lpm_counter_component|auto_generated 3 0 0 0 13 0 0 0 0 0 0 0 0
inst36|inst2 3 0 0 0 13 0 0 0 0 0 0 0 0
inst36|inst10|lpm_compare_component|auto_generated 27 0 0 0 1 0 0 0 0 0 0 0 0
inst36|inst10 27 0 0 0 1 0 0 0 0 0 0 0 0
inst36|inst4 2 0 0 0 1 0 0 0 0 0 0 0 0
inst36 371 224 0 224 273 224 224 224 0 0 0 0 0
inst57 392 267 2 267 269 267 267 267 32 0 0 0 0
inst81|inst7 33 0 0 0 32 0 0 0 0 0 0 0 0
inst81|inst8 33 0 0 0 32 0 0 0 0 0 0 0 0
inst81|inst3 33 0 0 0 32 0 0 0 0 0 0 0 0
inst81|inst5 33 0 0 0 32 0 0 0 0 0 0 0 0
inst81|inst1 33 0 0 0 32 0 0 0 0 0 0 0 0
inst81|inst2 33 0 0 0 32 0 0 0 0 0 0 0 0
inst81|inst22 33 0 0 0 32 0 0 0 0 0 0 0 0
inst81|inst23 33 0 0 0 32 0 0 0 0 0 0 0 0
inst81|inst19 33 0 0 0 32 0 0 0 0 0 0 0 0
inst81|inst20 33 0 0 0 32 0 0 0 0 0 0 0 0
inst81|inst16 33 0 0 0 32 0 0 0 0 0 0 0 0
inst81|inst17 33 0 0 0 32 0 0 0 0 0 0 0 0
inst81|inst13 33 0 0 0 32 0 0 0 0 0 0 0 0
inst81|inst14 33 0 0 0 32 0 0 0 0 0 0 0 0
inst81|inst10 33 0 0 0 32 0 0 0 0 0 0 0 0
inst81|inst11 33 0 0 0 32 0 0 0 0 0 0 0 0
inst81|inst61 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst62 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst58 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst59 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst55 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst56 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst52 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst53 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst49 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst50 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst46 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst47 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst43 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst44 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst40 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst41 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst37 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst38 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst34 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst35 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst31 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst32 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst28 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst29 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst25 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81|inst26 2 0 0 0 1 0 0 0 0 0 0 0 0
inst81 271 137 1 137 269 137 137 137 0 0 0 0 0
inst13 2 0 0 0 10 0 0 0 0 0 0 0 0
inst14 2 0 0 0 1 0 0 0 0 0 0 0 0
inst15 2 0 0 0 1 0 0 0 0 0 0 0 0
inst82 3 3 0 3 6 3 3 3 0 0 0 0 0
inst16 2 0 0 0 1 0 0 0 0 0 0 0 0
inst17 2 0 0 0 1 0 0 0 0 0 0 0 0
inst2|address_cnt|auto_generated 9 0 0 0 6 0 0 0 0 0 0 0 0
inst2|comp|auto_generated 20 0 0 0 1 0 0 0 0 0 0 0 0
inst2 54 1 1 1 33 1 1 1 2 0 0 0 2