Sample behavioral waveforms for design file pll_smal.vhd

The following waveforms show the behavior of altpll megafunction for the chosen set of parameters in design pll_smal.vhd. The design pll_smal.vhd has Stratix II Enhanced pll configured in NORMAL mode The primary clock input to the PLL is INCLK0, with clock period 8000 ps.

Fig. 1 : Wave showing NORMAL mode operation.