Schematics - Board  schematics in pdf format. 

Layout - Board fabrication and assembly documentation. 

FPGA Projects:

• OFC-2 QSFP Voltage Translator FPGA Design: OFC2_QSFP.zip - Quartus 18.1 STD Project and pin file

• OFC-2 Power Manager FPGA Design: OFC2_PWR.zip Quartus 18.1 STD Project and pin file

• OFC-2 VME Interface FPGA Design: OFC2_VME.zip Quartus 18.1 STD Projectand pin file

• OFC-2 VME Interface Simulation: VME_Test.zip Quartus 9.1 Project - Top_Level, Timing_Simulation, Do not use this on actual OFC2 Module.

• OFC-2 Data Processor FPGA Design: OFC2_S10.zip Quartus 19.2 PRO Project - Skeleton Project for pin assignment. Only VME Interface is Functional

• OFC-2 Data Processor FPGA Design: OFC2_S10_72.zip and OFC2_S10_72.qar - Quartus 21.2 PRO Project - Skeleton Project with 5Gbps transceivers, using only MGTREFCLK[2] and MGTREFCLK[6], and with HBM part removed: Pins CLK_HBM_TOP and CLK_HBM_BOT changed to GND+ (GND+ pin should connect to GND. It may also be connected to a valid signal on the board, if that signal is required for a different revision of the design.) This is the new OFC2_S10_72.sof and the new pin file

• OFC-2 Data Processor FPGA Design: OFC2_S10_68.zip and OFC2_S10_68.qar - Quartus 21.2 PRO Project - Skeleton Project with 5Gbps Transceiver Error Counter and with HBM part removed: Pins CLK_HBM_TOP and CLK_HBM_BOT changed to GND+ (GND+ pin should connect to GND. It may also be connected to a valid signal on the board, if that signal is required for a different revision of the design.)

• OFC-2 Data Processor FPGA Design: OFC2_S10_65.zip and OFC2_S10_65.qar - Quartus 21.2 PRO Project - Skeleton Project with 5Gbps transceivers and with HBM part removed: Pins CLK_HBM_TOP and CLK_HBM_BOT changed to GND+ (GND+ pin should connect to GND. It may also be connected to a valid signal on the board, if that signal is required for a different revision of the design.) This is the new pin file

• OFC-2 Data Processor FPGA Design: OFC2_S10_54.zip and OFC2_S10_54.qar - Quartus 21.2 PRO Project - Skeleton Project with HBM part removed: Pins CLK_HBM_TOP and CLK_HBM_BOT changed to GND+ (GND+ pin should connect to GND. It may also be connected to a valid signal on the board, if that signal is required for a different revision of the design.) This is the new pin file

• Testing Instructions for the OFC1-OFC2 5Gbps communications

• Installation Instructions.

• I2C .

Related materials

• OFC2_StatusReport_6_11_2020.pdf

• OFC2_StatusRepoer_3_12_2020.pdf

• C2.zip Preliminary S10 Quartus Project
• HBM_TOP.zip and HBM_TOP.qar - Quartus generated example designs for the Stratix10 HBM Top side
• HBM_BOT.zip and HBM_BOT.qar - Quartus generated example designs for the Stratix10 HBM Bottom side
• ArriaV_2xSFPs.zip and ArriaV_2xSFPs.qar - Quartus 15.0 example design with Arria V. This designs only has two transceivers, with working settings.
• S10_4xSFPs.zip and S10_4xSFPs.qar - Quartus 19.2 PRO example design with Stratix 10 Mx. This design only has 4 transceivers, that should be set to match the ArriaV_2xSFPs design.
• Smoke Test

Updated: February, 2023