Trace Analysis

1. CDFclkBus0_0.pdf
2. CDFclkBus0_1.pdf
3. CDFclkBus0_2.pdf
4. Logic1_F1data0.pdf
5. Logic1_F1data1.pdf
6. Logic1_F1data30.pdf
7. Logic1_F1data31.pdf
8. Logic2_F2data0.pdf
9. Logic2_F2data1.pdf
10. Logic2_F2data30.pdf
11. Logic2_F2data31.pdf
12. Logic1_FIFO_emptyA0_n.pdf
13. Logic1_FIFO_emptyA1_n.pdf
14. Logic1_FIFO_emptyA2_n.pdf
15. Logic1_FIFO_emptyA3_n.pdf
16. Logic1_FIFO_emptyB0_n.pdf
17. Logic1_FIFO_emptyB1_n.pdf
18. Logic1_FIFO_emptyB2_n.pdf
19. Logic1_FIFO_emptyB3_n.pdf
20. Logic1_FPGASVT_Ctrl_rdclk.pdf
21. Logic1_FPGAWRclkA.pdf
22. Logic1_FPGAWRclkB.pdf
23. Logic1_L1_IN_DS_0.pdf
24. Logic1_L1_IN_DS_1.pdf
25. Logic1_LCLK1.pdf
26. Logic1_LCLK2.pdf
27. Logic1_LCTRL1_n_in.pdf
28. Logic1_LCTRL2_n_in.pdf
29. Logic1_LWEN1_n_in.pdf
30. Logic1_LWEN2_n_in.pdf
31. Logic1_Roboclock.pdf
32. Logic1_SLINK40MHzClk.pdf
33. Logic1_SRAM_Clk.pdf
34. Logic1_SVT_Ctrl_reset.pdf
35. Logic1_SVT_IN0.pdf
36. Logic1_SVT_IN22.pdf
37. Logic1_SVT_status_DS_n.pdf
38. Logic1_SVT_status_afull_n.pdf
39. Logic1_SVT_status_empty0_n.pdf
40. Logic1_SVT_status_empty1_n.pdf
41. Logic1_SVT_status_full_n.pdf
42. Logic1_UCLK.pdf
43. Logic1_UCTRL_n.pdf
44. Logic1_UWEN_n.pdf