Schematics of the TDC board
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sheet1.pdf : Top level diagram
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sheet2.pdf : VME_Interface
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sheet3.pdf : VME-P1
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sheet4.pdf : VME-Chip
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sheet5.pdf : VME-P0
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sheet6.pdf : VME-P2
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sheet7.pdf : FP Connector
1
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sheet8.pdf : FP Connector
2
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sheet9.pdf : Stratix Chip
0
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sheet10.pdf : Clock Buffer
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sheet11.pdf : ID_SW &
Test Conn
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sheet12.pdf : Power
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sheet13.pdf : FP Connector
3
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sheet14.pdf : P3 Connector
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sheet15.pdf : Stratix Chip
1
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sheet16.pdf : FP Connector
4
For questions regarding this page contact Mircea Bogdan.
bogdan@frodo.uchicago.edu
Revised: Jan. 2004