More TDC Tests using the Altera FPGA Development Board 5QV1


July 8, 2004:
 

Using our Altera FPGA Development Board Q5V1 by Rowe Engineering, we implemented a 12 channel LVDS Test Pulse Generator (TPG) with the following pattern:
 

  • Wire0:     ...,8 bits - ON, 3 bits - OFF, 8 bits - ON, 3 bits - OFF,...
  • Wire1:     ...,3 bits - ON, 8 bits - OFF, 3 bits - ON, 8 bits - OFF,...
  • Wire2:     ...,7 bits - ON, 4 bits - OFF, 7 bits - ON, 4 bits - OFF,...
  • Wire3:     ...,4 bits - ON, 7 bits - OFF, 4 bits - ON, 7 bits - OFF,...
  • Wire4:     ...,6 bits - ON, 5 bits - OFF, 6 bits - ON, 5 bits - OFF,...
  • Wire5:     ...,5 bits - ON, 6 bits - OFF, 5 bits - ON, 6 bits - OFF,...
  • Wire6:     ...,9 bits - ON, 2 bits - OFF, 9 bits - ON, 2 bits - OFF,...
  • Wire7:     ...,4 bits - ON, 7 bits - OFF, 4 bits - ON, 7 bits - OFF,...
  • Wire8:     ...,7 bits - ON, 4 bits - OFF, 7 bits - ON, 4 bits - OFF,...
  • Wire9:     ...,2 bits - ON, 9 bits - OFF, 2 bits - ON, 9 bits - OFF,...
  • Wire10:   ...,6 bits - ON, 5 bits - OFF, 6 bits - ON, 5 bits - OFF,...
  • Wire11:   ...,5 bits - ON, 6 bits - OFF, 5 bits - ON, 6 bits - OFF,...


    • Here's a simulation of the outputs for Wire11..0, as seen in QuartusII.
    This pattern is not in phase with the CDF Clock but it repeats itself in a continuous flow.

    Test procedure:
    Plugged TPG to the TDC Board FP2. (Wire_0 -> TDC_Channel_35, Wire_1 -> TDC_Channel_34,...,Wire_11 -> TDC_Channel_24)
    Plugged connectors with the negative inputs shortened to GND to FP1, Fp3, FP4. (TDC_Channel_95,...36,23,...0 = High.)
    Generated one L1A pulse with the Test-Clock Board and one L2A pulse via VME.
    Compared the TDC-measured pulse widths and time intervals between pulses with the TPG pattern.
    Repeated the L1A/L2A succesion 12 times.
    This transcript presents the VME comands as well as the Hit Count and Hit Data info from the board's VME readout buffer.

    Results:
    From these tests,  we conclude that the minimum pulse width is 4.8ns (4 bits) +/- 0.6ns (1/2 bit)
    and the double pulse resolution (minimum interval between pulses) is also 4.8ns (4 bits) +/- 0.6ns (1/2 bit).

    Observation:
    As expected, some half the time in this test setup, the TDC receiver drops a bit from a pulse. Some times it picks a bit.
    We learned from previous experiments with our TPG that a 4-bit (4.8ns) generated pulse may be seen as a 3-bit pulse by the TDC receiver and not be recorded as a hit at all.
     
     


     
     
    For questions regarding this page contact Mircea Bogdan.
    bogdan@frodo.uchicago.edu