Schematics of the DAMIC - Acquisition and Control Module

1. B3018_1.pdf : Top level diagram of the DAMIC - ACM;
2. B3018_2.pdf : Digital Input and Clocks;
3. B3018_3.pdf : ADC Block;
4. B3018_4_1.pdf, B3018_4_2.pdf, B3018_4_3.pdf, B3018_4_4.pdf: ADC Channel (There are four identical channels);
5. B3018_5.pdf : Power Block;
6. B3018_6.pdf : FPGA;
7. B3018_7.pdf : FPGA Decoupling Circuit;
8. B3018_8.pdf : VME Block;
9. B3018_9.pdf : VME - P1;
10. B3018_10.pdf : VME-P2;
11. B3018_11.pdf : Ethernet Block;
12. B3018_12_1.pdf, B3018_12_2.pdf : SFP Block (There are two identical channels);
13. B3018_13.pdf : CCD Control Block;
14. B3018_14.pdf : DAC;
15. B3018_15_1.pdf, B3018_15_2.pdf, B3018_15_3.pdf, B3018_15_4.pdf, B3018_15_5.pdf: Clock Generator Block (There are five identical channels);
16. B3018_16.pdf : VSUB Generator Block;
17. B3018_17_1.pdf, B3018_17_2.pdf, B3018_17_3.pdf, B3018_17_4.pdf : Bias Generator Block (There are four identical channels);
18. B3018_18_1.pdf, B3018_18_2.pdf: Bias Generator with Offset Block (There are two identical channels);
19. B3018_19.pdf: CCD Connector Block

Revised: July 2022