Clock Distribution and Trigger (CDT) Processor Module for KOTO
Schematics - Board
schematics
in pdf format.
Layout - Board fabrication
and assembly documentation.
Related materials
-
CDT FPGA_Design: CDT_Module_4.zip This Firmware has a constant Fan-Out Delay of ~10ns.
-
CDT FPGA_Design: CDT_Module_5.zip This Firmware has a adjustable Fan-Out Delay between 11ns and 33ns, in steps of 4ns.
-
- StatusReport_2_23_2017.ppt, StatusReport_2_23_2017.pdf
- StatusReport_10_13_2016.ppt, StatusReport_10_13_2016.pdf
- Crate Distribution and Trigger Processing Module for the KOTO Experiment, Mircea Bogdan, Yuting Luo, Yu-Chen Tung, Yau Wah - TIPP, May 22-26, 2017 Beijing, People's Republic of China, Poster.pdf
- 2016KOTO Collaboration Meeting Presentation, August 26-28, 2016, J-PARC, Japan - NEW_CDT_Module.ppt, NEW_CDT_Module.pdf
For questions regarding this page contact
Mircea Bogdan.
bogdan@edg.uchicago.edu
Updated: October 2021