CAPMAP DAQ CONTROLLER (A2524)


Capmap DAQ Controller (A2524) Design Files    
Schematics
Artworks    

Assembly Drawings Amphenol Connector, J6, J7, J8, J9 Signal Definitions
Assembly list    

2524 PCB  Manufacturing Data Files  for  PCB  House  
Specifications  
Layer  Stack-up Order and Trace Impedance Control  
Manufacturing Data Files (.zip)  

ATERA FPGA (EP20K160EQC208-3) Design Files  
Pin Definitions  
Configuration (.pof)  
     
     

Other Files  
Apex 20KE  Programble Logic Device Data Sheet  
Altera Device Package Information Data Sheet  
Configuration Devices for SRAM-Based LUT Devices Data Sheet  
EP20K160E Pin Table  
Apex 20KE IBIS Model (I/O=LVTTL)  
Quad LVDS line receiver (DS90LV031A)  
Quad LVDS line driver (DS90LV032A)  
   
   

Contact person:
Fukun Tang Electronics Development Group University of Chicago (773)-702-7801