Schematics (#2958_1,...,20 Rev.A)

  1. 2958_Sheet_1.pdf: Top Level
  2. 2958_Sheet_2.pdf: Power Tree
  3. 2958_Sheet_3.pdf: Power Block
  4. 2958_Sheet_4.pdf: Power 3.3V AUX
  5. 2958_Sheet_5.pdf: Power VCCIO-UIB - 1.2V
  6. 2958_Sheet_6.pdf: Power Core VCC - 0.9V VIB
  7. 2958_Sheet_7.pdf: Power SENSE
  8. 2958_Sheet_8_1.pdf: Power VCCERAM - 0.9V
  9. 2958_Sheet_8_2.pdf: Power VCCRL - 1.03V
  10. 2958_Sheet_8_4.pdf: Power VCCT - 1.03V
  11. 2958_Sheet_8_5.pdf: Power VCCH-GXB - 1.8V
  12. 2958_Sheet_9.pdf: Power VCCM - 2.5V
  13. 2958_Sheet_10.pdf: Power Manager - MAX10
  14. 2958_Sheet_11.pdf: VME Interface Block
  15. 2958_Sheet_12.pdf: VME Interface P2
  16. 2958_Sheet_13.pdf: VME Interface P1
  17. 2958_Sheet_14.pdf: VME Interface FPGA MAX10
  18. 2958_Sheet_15.pdf: VME Data Internal Buffer
  19. 2958_Sheet_16.pdf: VME Local Busl Buffer
  20. 2958_Sheet_17_1.pdf: QSFP Block 0-2
  21. 2958_Sheet_17_2.pdf: QSFP Block 3-5
  22. 2958_Sheet_17_3.pdf: QSFP Block 6-8
  23. 2958_Sheet_18_1.pdf: FPGA STRATIX10MX - Sheet 1
  24. 2958_Sheet_18_2.pdf: FPGA STRATIX10MX - Sheet 2
  25. 2958_Sheet_18_3.pdf: FPGA STRATIX10MX/QSFP Control Buffers - MAX10
  26. 2958_Sheet_18_4.pdf: FPGA STRATIX10MX - Sheet 4
  27. 2958_Sheet_19.pdf: FPGA STRATIX10MX Decoupling Caps
  28. 2958_Sheet_20.pdf: Clocks

     

     


 
For questions regarding this page contact Mircea Bogdan.
bogdan@edg.uchicago.edu

Revised: October 2020